XC17128D-PD8C vs MCP17128CN feature comparison

XC17128D-PD8C AMD Xilinx

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MCP17128CN Motorola Mobility LLC

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Rohs Code No
Part Life Cycle Code Obsolete Obsolete
Ihs Manufacturer XILINX INC MOTOROLA INC
Part Package Code DIP DIP
Package Description DIP, DIP8,.3 DIP,
Pin Count 8 8
Reach Compliance Code compliant unknown
Additional Feature USED FOR STORING THE CONFIGURATION BITSTREAMS OF XILINX FPGAS
Clock Frequency-Max (fCLK) 12.5 MHz
I/O Type COMMON
JESD-30 Code R-PDIP-T8 R-PDIP-T8
JESD-609 Code e0
Length 9.3599 mm 9.78 mm
Memory Density 131072 bit 131072 bit
Memory IC Type CONFIGURATION MEMORY OTP ROM
Memory Width 1 1
Moisture Sensitivity Level 1
Number of Functions 1 1
Number of Terminals 8 8
Number of Words 131072 words 131072 words
Number of Words Code 128000 128000
Operating Mode SYNCHRONOUS SYNCHRONOUS
Operating Temperature-Max 70 °C 70 °C
Operating Temperature-Min
Organization 128KX1 128KX1
Output Characteristics 3-STATE 3-STATE
Package Body Material PLASTIC/EPOXY PLASTIC/EPOXY
Package Code DIP DIP
Package Equivalence Code DIP8,.3
Package Shape RECTANGULAR RECTANGULAR
Package Style IN-LINE IN-LINE
Parallel/Serial SERIAL SERIAL
Power Supplies 5 V
Qualification Status Not Qualified Not Qualified
Seated Height-Max 4.5974 mm 4.45 mm
Standby Current-Max 0.00005 A
Supply Current-Max 0.01 mA
Supply Voltage-Max (Vsup) 5.25 V 6 V
Supply Voltage-Min (Vsup) 4.75 V 4.5 V
Supply Voltage-Nom (Vsup) 5 V 5 V
Surface Mount NO NO
Technology CMOS CMOS
Temperature Grade COMMERCIAL COMMERCIAL
Terminal Finish Tin/Lead (Sn85Pb15)
Terminal Form THROUGH-HOLE THROUGH-HOLE
Terminal Pitch 2.54 mm 2.54 mm
Terminal Position DUAL DUAL
Width 7.62 mm 7.62 mm
Base Number Matches 1 2
ECCN Code EAR99
HTS Code 8542.32.00.71

Compare XC17128D-PD8C with alternatives

Compare MCP17128CN with alternatives