UPD30410LRP-50
vs
TSX68040VR33
feature comparison
All Stats
Differences Only
Pbfree Code
Rohs Code
Part Life Cycle Code
Obsolete
Obsolete
Ihs Manufacturer
NEC ELECTRONICS CORP
THOMSON-CSF SEMICONDUCTORS
Part Package Code
PGA
PGA
Package Description
HPGA,
,
Pin Count
179
179
Reach Compliance Code
compliant
unknown
ECCN Code
3A991.A.2
3A991.A.2
HTS Code
8542.31.00.01
8542.31.00.01
Additional Feature
8 PIPELINE STAGES; MMU WITH 48 ENTRY TLB; OPTEMP SPECIFIED AS TC
Address Bus Width
64
32
Bit Size
64
32
Boundary Scan
YES
YES
Clock Frequency-Max
50 MHz
33 MHz
External Data Bus Width
64
32
Format
FLOATING POINT
FIXED POINT
Integrated Cache
NO
YES
JESD-30 Code
S-CPGA-P179
S-CPGA-P179
JESD-609 Code
e0
Length
47.24 mm
Low Power Mode
NO
Number of Terminals
179
179
Operating Temperature-Max
80 °C
Operating Temperature-Min
-40 °C
Package Body Material
CERAMIC, METAL-SEALED COFIRED
CERAMIC, METAL-SEALED COFIRED
Package Code
HPGA
PGA
Package Shape
SQUARE
SQUARE
Package Style
GRID ARRAY, HEAT SINK/SLUG
GRID ARRAY
Qualification Status
Not Qualified
Not Qualified
Seated Height-Max
11.69 mm
Speed
100 MHz
33 MHz
Supply Voltage-Max
3.465 V
5.25 V
Supply Voltage-Min
3.135 V
4.75 V
Supply Voltage-Nom
3.3 V
5 V
Surface Mount
NO
NO
Technology
CMOS
HCMOS
Temperature Grade
COMMERCIAL EXTENDED
Terminal Finish
TIN LEAD
Terminal Form
PIN/PEG
PIN/PEG
Terminal Pitch
2.54 mm
Terminal Position
PERPENDICULAR
PERPENDICULAR
Width
47.24 mm
uPs/uCs/Peripheral ICs Type
MICROPROCESSOR, RISC
MICROPROCESSOR
Base Number Matches
1
1
Compare UPD30410LRP-50 with alternatives
Compare TSX68040VR33 with alternatives