SI7450DP-T1-GE3
vs
SI7450DP-T1-E3
feature comparison
| Pbfree Code |
Yes
|
|
| Part Life Cycle Code |
Active
|
Active
|
| Ihs Manufacturer |
VISHAY SILICONIX
|
VISHAY INTERTECHNOLOGY INC
|
| Part Package Code |
SOT
|
|
| Package Description |
SMALL OUTLINE, R-XDSO-C5
|
|
| Pin Count |
8
|
|
| Reach Compliance Code |
unknown
|
compliant
|
| ECCN Code |
EAR99
|
EAR99
|
| Samacsys Manufacturer |
Vishay
|
Vishay
|
| Case Connection |
DRAIN
|
DRAIN
|
| Configuration |
SINGLE WITH BUILT-IN DIODE
|
SINGLE WITH BUILT-IN DIODE
|
| DS Breakdown Voltage-Min |
200 V
|
200 V
|
| Drain Current-Max (ID) |
3.2 A
|
3.2 A
|
| Drain-source On Resistance-Max |
0.09 Ω
|
0.09 Ω
|
| FET Technology |
METAL-OXIDE SEMICONDUCTOR
|
METAL-OXIDE SEMICONDUCTOR
|
| JESD-30 Code |
R-XDSO-C5
|
R-XDSO-C5
|
| JESD-609 Code |
e3
|
e3
|
| Moisture Sensitivity Level |
1
|
1
|
| Number of Elements |
1
|
1
|
| Number of Terminals |
5
|
5
|
| Operating Mode |
ENHANCEMENT MODE
|
ENHANCEMENT MODE
|
| Operating Temperature-Max |
150 °C
|
150 °C
|
| Package Body Material |
UNSPECIFIED
|
UNSPECIFIED
|
| Package Shape |
RECTANGULAR
|
RECTANGULAR
|
| Package Style |
SMALL OUTLINE
|
SMALL OUTLINE
|
| Peak Reflow Temperature (Cel) |
260
|
260
|
| Polarity/Channel Type |
N-CHANNEL
|
N-CHANNEL
|
| Power Dissipation-Max (Abs) |
5.2 W
|
5.2 W
|
| Pulsed Drain Current-Max (IDM) |
40 A
|
40 A
|
| Qualification Status |
Not Qualified
|
Not Qualified
|
| Surface Mount |
YES
|
YES
|
| Terminal Finish |
Matte Tin (Sn) - annealed
|
Matte Tin (Sn)
|
| Terminal Form |
C BEND
|
C BEND
|
| Terminal Position |
DUAL
|
DUAL
|
| Time@Peak Reflow Temperature-Max (s) |
30
|
30
|
| Transistor Application |
SWITCHING
|
SWITCHING
|
| Transistor Element Material |
SILICON
|
SILICON
|
| Base Number Matches |
2
|
2
|
| Rohs Code |
|
Yes
|
|
|
|
Compare SI7450DP-T1-GE3 with alternatives
Compare SI7450DP-T1-E3 with alternatives