HD74ALVC1G80VS-E vs HD74ALVC1G80VSE feature comparison

HD74ALVC1G80VS-E Hitachi Ltd

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HD74ALVC1G80VSE Renesas Electronics Corporation

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Rohs Code Yes Yes
Part Life Cycle Code Transferred Active
Ihs Manufacturer HITACHI LTD RENESAS ELECTRONICS CORP
Part Package Code SON SON
Package Description VSOF, FL6,.047,20 VSOF, FL6,.047,20
Pin Count 5 5
Reach Compliance Code unknown compliant
HTS Code 8542.39.00.01 8542.39.00.01
Family ALVC/VCX/A ALVC/VCX/A
JESD-30 Code R-PDSO-F5 R-PDSO-F5
Length 1.6 mm 1.6 mm
Load Capacitance (CL) 30 pF 30 pF
Logic IC Type D FLIP-FLOP D FLIP-FLOP
Max Frequency@Nom-Sup 200000000 Hz 200000000 Hz
Max I(ol) 0.024 A 0.024 A
Number of Bits 1 1
Number of Functions 1 1
Number of Terminals 5 5
Operating Temperature-Max 85 °C 85 °C
Operating Temperature-Min -40 °C -40 °C
Output Polarity INVERTED INVERTED
Package Body Material PLASTIC/EPOXY PLASTIC/EPOXY
Package Code VSOF VSOF
Package Equivalence Code FL6,.047,20 FL6,.047,20
Package Shape RECTANGULAR RECTANGULAR
Package Style SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE
Packing Method TR TR
Prop. Delay@Nom-Sup 3 ns 3 ns
Propagation Delay (tpd) 8 ns 8 ns
Qualification Status Not Qualified Not Qualified
Seated Height-Max 0.6 mm 0.6 mm
Supply Voltage-Max (Vsup) 3.6 V 3.6 V
Supply Voltage-Min (Vsup) 1.2 V 1.2 V
Supply Voltage-Nom (Vsup) 1.5 V 1.5 V
Surface Mount YES YES
Technology CMOS CMOS
Temperature Grade INDUSTRIAL INDUSTRIAL
Terminal Form FLAT FLAT
Terminal Pitch 0.5 mm 0.5 mm
Terminal Position DUAL DUAL
Trigger Type POSITIVE EDGE POSITIVE EDGE
Width 1.2 mm 1.2 mm
fmax-Min 200 MHz 200 MHz
Base Number Matches 2 1
Pbfree Code No
JESD-609 Code e0
Peak Reflow Temperature (Cel) NOT SPECIFIED
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED

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Compare HD74ALVC1G80VSE with alternatives