Parametric results for: xc5202-4pcg84i under Field Programmable Gate Arrays

All Filters Additional Feature Clock Frequency-Max Combinatorial Delay of a CLB-Max JESD-30 Code JESD-609 Code Length Manufacturer Moisture Sensitivity Level Number of CLBs Number of Equivalent Gates Number of Terminals Organization Package Body Material Package Code Package Shape Package Style Part Life Cycle Code Pbfree Code Peak Reflow Temperature (Cel) Programmable Logic Type Qualification Status Rohs Code Seated Height-Max Supply Voltage-Max Supply Voltage-Min Supply Voltage-Nom Surface Mount Technology Terminal Finish Terminal Form

TYP. GATES = 2000-3000 1

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83 MHz 1

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Combinatorial Delay of a CLB-Max (1)

3.8 ns 1

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S-PQCC-J84 1

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e3 1

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29.3116 mm 1

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Manufacturer (1)

AMD Xilinx 1

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3 1

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Number of CLBs (1)

64 1

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Number of Equivalent Gates (1)

2000 1

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84 1

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64 CLBS, 2000 GATES 1

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PLASTIC/EPOXY 1

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QCCJ 1

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Package Shape (1)

SQUARE 1

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CHIP CARRIER 1

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Obsolete 1

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Yes 1

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245 1

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Programmable Logic Type (1)

FIELD PROGRAMMABLE GATE ARRAY 1

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Not Qualified 1

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Yes 1

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5.08 mm 1

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5.5 V 1

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4.5 V 1

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Supply Voltage-Nom (1)

5 V 1

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YES 1

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CMOS 1

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Matte Tin (Sn) 1

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J BEND 1

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