Parametric results for: xc2vpx20-5ffg896c under Field Programmable Gate Arrays

All Filters Clock Frequency-Max Combinatorial Delay of a CLB-Max JESD-30 Code JESD-609 Code Length Manufacturer Moisture Sensitivity Level Number of CLBs Number of Inputs Number of Logic Cells Number of Outputs Number of Terminals Operating Temperature-Max Operating Temperature-Min Organization Package Body Material Package Code Package Equivalence Code Package Shape Package Style Part Life Cycle Code Peak Reflow Temperature (Cel) Programmable Logic Type Qualification Status Rohs Code Seated Height-Max Supply Voltage-Max Supply Voltage-Min Supply Voltage-Nom Surface Mount Technology Temperature Grade Terminal Finish Terminal Form

1.05 GHz 1

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Combinatorial Delay of a CLB-Max (1)

360 ps 1

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S-PBGA-B896 1

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e1 1

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31 mm 1

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Manufacturer (1)

AMD Xilinx 1

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4 1

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Number of CLBs (1)

2448 1

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Number of Inputs (1)

552 1

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Number of Logic Cells (1)

22032 1

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Number of Outputs (1)

552 1

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896 1

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85.0 °C 1

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0.0 °C 1

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2448 CLBS 1

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PLASTIC/EPOXY 1

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BGA 1

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BGA896,30X30,40 1

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Package Shape (1)

SQUARE 1

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GRID ARRAY 1

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Obsolete 1

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245 1

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Programmable Logic Type (1)

FIELD PROGRAMMABLE GATE ARRAY 1

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Not Qualified 1

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Yes 1

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3.4 mm 1

1 hit Apply

1.575 V 1

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1.425 V 1

1 hit Apply

Supply Voltage-Nom (1)

1.5 V 1

1 hit Apply

YES 1

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CMOS 1

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Temperature Grade (1)

OTHER 1

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Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5) 1

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BALL 1

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