Parametric results for: sn74lvc112apwe4 under FF/Latches

All Filters Family JESD-30 Code JESD-609 Code Length Load Capacitance (CL) Logic IC Type Manufacturer Max Frequency@Nom-Sup Max I(ol) Moisture Sensitivity Level Number of Bits Number of Functions Number of Terminals Operating Temperature-Max Operating Temperature-Min Output Polarity Package Body Material Package Code Package Equivalence Code Package Shape Package Style Prop. Delay@Nom-Sup Propagation Delay (tpd) Supply Voltage-Nom (Vsup) Surface Mount Trigger Type Family (1)

LVC/LCX/Z 1

1 hit Apply

R-PDSO-G16 1

1 hit Apply

e4 1

1 hit Apply

5 mm 1

1 hit Apply

Load Capacitance (CL) (1)

50 pF 1

1 hit Apply

J-K FLIP-FLOP 1

1 hit Apply

Manufacturer (1)

Texas Instruments 1

1 hit Apply

Max Frequency@Nom-Sup (1)

150 MHz 1

1 hit Apply

24 mA 1

1 hit Apply

1 1

1 hit Apply

Number of Bits (1)

2 1

1 hit Apply

Number of Functions (1)

2.0 1

1 hit Apply

16 1

1 hit Apply

125.0 °C 1

1 hit Apply

-40.0 °C 1

1 hit Apply

COMPLEMENTARY 1

1 hit Apply

PLASTIC/EPOXY 1

1 hit Apply

Package Code (1)

TSSOP 1

1 hit Apply

TSSOP16,.25 1

1 hit Apply

RECTANGULAR 1

1 hit Apply

SMALL OUTLINE, THIN PROFILE, SHRINK PITCH 1

1 hit Apply

Prop. Delay@Nom-Sup (1)

5.9 ns 1

1 hit Apply

Propagation Delay (tpd) (1)

7.1 ns 1

1 hit Apply

Supply Voltage-Nom (Vsup) (1)

1.8 V 1

1 hit Apply

Surface Mount (1)

YES 1

1 hit Apply

Trigger Type (1)

NEGATIVE EDGE 1

1 hit Apply