Parametric results for: XC7S15-2TQGA144I under Field Programmable Gate Arrays

All Filters Combinatorial Delay of a CLB-Max JESD-30 Code Manufacturer Number of CLBs Number of Terminals Organization Package Body Material Package Code Package Shape Package Style Part Life Cycle Code Peak Reflow Temperature (Cel) Programmable Logic Type Rohs Code Supply Voltage-Max Supply Voltage-Min Supply Voltage-Nom Surface Mount Terminal Form Combinatorial Delay of a CLB-Max (1)

1.05 ns 2

2 hits Apply

S-PBGA-B144 2

2 hits Apply

Manufacturer (2)

AMD 1 AMD Xilinx 1

2 hits Apply

Number of CLBs (1)

1000 2

2 hits Apply

144 2

2 hits Apply

1000 CLBS 2

2 hits Apply

PLASTIC/EPOXY 2

2 hits Apply

BGA 2

2 hits Apply

Package Shape (1)

SQUARE 2

2 hits Apply

GRID ARRAY 2

2 hits Apply

Active 1 Transferred 1

2 hits Apply

NOT SPECIFIED 2

2 hits Apply

Programmable Logic Type (1)

FIELD PROGRAMMABLE GATE ARRAY 2

2 hits Apply

Yes 2

2 hits Apply

1.05 V 2

2 hits Apply

950 mV 2

2 hits Apply

Supply Voltage-Nom (1)

1 V 2

2 hits Apply

YES 2

2 hits Apply

BALL 2

2 hits Apply