Parametric results for: XC5VLX50T-3FFG665C under Field Programmable Gate Arrays

All Filters Combinatorial Delay of a CLB-Max JESD-30 Code JESD-609 Code Length Manufacturer Moisture Sensitivity Level Number of CLBs Number of Inputs Number of Logic Cells Number of Outputs Number of Terminals Operating Temperature-Max Operating Temperature-Min Organization Package Body Material Package Code Package Equivalence Code Package Shape Package Style Part Life Cycle Code Peak Reflow Temperature (Cel) Programmable Logic Type Qualification Status Rohs Code Seated Height-Max Supply Voltage-Max Supply Voltage-Min Supply Voltage-Nom Surface Mount Temperature Grade Terminal Finish Terminal Form Combinatorial Delay of a CLB-Max (1)

670 ps 1

1 hit Apply

S-PBGA-B665 1

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e1 1

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27 mm 1

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Manufacturer (1)

AMD Xilinx 1

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4 1

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Number of CLBs (1)

3600 1

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Number of Inputs (1)

360 1

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Number of Logic Cells (1)

46080 1

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Number of Outputs (1)

360 1

1 hit Apply

665 1

1 hit Apply

85.0 °C 1

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0.0 °C 1

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3600 CLBS 1

1 hit Apply

PLASTIC/EPOXY 1

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BGA 1

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BGA665,26X26,40 1

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Package Shape (1)

SQUARE 1

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GRID ARRAY 1

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Transferred 1

1 hit Apply

250 1

1 hit Apply

Programmable Logic Type (1)

FIELD PROGRAMMABLE GATE ARRAY 1

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Not Qualified 1

1 hit Apply

Yes 1

1 hit Apply

2.9 mm 1

1 hit Apply

10.5 V 1

1 hit Apply

950 mV 1

1 hit Apply

Supply Voltage-Nom (1)

1 V 1

1 hit Apply

YES 1

1 hit Apply

Temperature Grade (1)

OTHER 1

1 hit Apply

TIN SILVER COPPER 1

1 hit Apply

BALL 1

1 hit Apply