Parametric results for: XC4085XLA-09BGG560I under Field Programmable Gate Arrays

All Filters Additional Feature Clock Frequency-Max Combinatorial Delay of a CLB-Max JESD-30 Code JESD-609 Code Length Manufacturer Moisture Sensitivity Level Number of CLBs Number of Equivalent Gates Number of Terminals Organization Package Body Material Package Code Package Shape Package Style Part Life Cycle Code Pbfree Code Peak Reflow Temperature (Cel) Programmable Logic Type Qualification Status Rohs Code Seated Height-Max Supply Voltage-Max Supply Voltage-Min Supply Voltage-Nom Surface Mount Technology Terminal Finish Terminal Form

CAN ALSO USE 180000 GATES 1

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227 MHz 1

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Combinatorial Delay of a CLB-Max (1)

1.1 ns 1

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S-PBGA-B560 1

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e1 1

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42.5 mm 1

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Manufacturer (1)

AMD Xilinx 1

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3 1

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Number of CLBs (1)

3136 1

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Number of Equivalent Gates (1)

55000 1

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560 1

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3136 CLBS, 55000 GATES 1

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PLASTIC/EPOXY 1

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LBGA 1

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Package Shape (1)

SQUARE 1

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GRID ARRAY, LOW PROFILE 1

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Obsolete 1

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Yes 1

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260 1

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Programmable Logic Type (1)

FIELD PROGRAMMABLE GATE ARRAY 1

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Not Qualified 1

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Yes 1

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1.7 mm 1

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3.6 V 1

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3 V 1

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Supply Voltage-Nom (1)

3.3 V 1

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YES 1

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CMOS 1

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Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5) 1

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BALL 1

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