Parametric results for: XC4020XLA-9PQ240I under Field Programmable Gate Arrays

All Filters Clock Frequency-Max Combinatorial Delay of a CLB-Max JESD-30 Code JESD-609 Code Length Manufacturer Moisture Sensitivity Level Number of CLBs Number of Equivalent Gates Number of Terminals Organization Package Body Material Package Code Package Shape Package Style Part Life Cycle Code Peak Reflow Temperature (Cel) Programmable Logic Type Qualification Status Rohs Code Seated Height-Max Supply Voltage-Max Supply Voltage-Min Supply Voltage-Nom Surface Mount Technology Terminal Finish Terminal Form

227 MHz 1

1 hit Apply

Combinatorial Delay of a CLB-Max (1)

1.1 ns 1

1 hit Apply

S-PQFP-G240 1

1 hit Apply

e0 1

1 hit Apply

32 mm 1

1 hit Apply

Manufacturer (1)

AMD Xilinx 1

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3 1

1 hit Apply

Number of CLBs (1)

784 1

1 hit Apply

Number of Equivalent Gates (1)

13000 1

1 hit Apply

240 1

1 hit Apply

784 CLBS, 13000 GATES 1

1 hit Apply

PLASTIC/EPOXY 1

1 hit Apply

FQFP 1

1 hit Apply

Package Shape (1)

SQUARE 1

1 hit Apply

FLATPACK, FINE PITCH 1

1 hit Apply

Obsolete 1

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NOT SPECIFIED 1

1 hit Apply

Programmable Logic Type (1)

FIELD PROGRAMMABLE GATE ARRAY 1

1 hit Apply

Not Qualified 1

1 hit Apply

No 1

1 hit Apply

4.1 mm 1

1 hit Apply

3.6 V 1

1 hit Apply

3 V 1

1 hit Apply

Supply Voltage-Nom (1)

3.3 V 1

1 hit Apply

YES 1

1 hit Apply

CMOS 1

1 hit Apply

Tin/Lead (Sn/Pb) 1

1 hit Apply

GULL WING 1

1 hit Apply