Parametric results for: XC3030-50PC68C under Field Programmable Gate Arrays

All Filters Additional Feature Clock Frequency-Max Combinatorial Delay of a CLB-Max JESD-30 Code JESD-609 Code Length Manufacturer Moisture Sensitivity Level Number of CLBs Number of Equivalent Gates Number of Inputs Number of Logic Cells Number of Outputs Number of Terminals Operating Temperature-Max Operating Temperature-Min Organization Package Body Material Package Code Package Equivalence Code Package Shape Package Style Part Life Cycle Code Programmable Logic Type Qualification Status Rohs Code Seated Height-Max Supply Voltage-Max Supply Voltage-Min Supply Voltage-Nom Surface Mount Technology Temperature Grade Terminal Finish Terminal Form

MAX 58 I/OS; 360 FLIP-FLOPS 1 MAX 58 I/OS; 360 FLIP-FLOPS; POWER-DOWN SUPPLY CURRENT = 2UA @ VCC = 3.2V & T = 25DEG CEL 2

3 hits Apply

50 MHz 3

3 hits Apply

Combinatorial Delay of a CLB-Max (1)

14 ns 1

3 hits Apply

S-PQCC-J68 3

3 hits Apply

e0 2

3 hits Apply

24.2316 mm 3

3 hits Apply

Manufacturer (1)

AMD Xilinx 3

3 hits Apply

1 1

3 hits Apply

Number of CLBs (1)

100 3

3 hits Apply

Number of Equivalent Gates (1)

3000 3

3 hits Apply

Number of Inputs (1)

58 1

3 hits Apply

Number of Logic Cells (1)

100 1

3 hits Apply

Number of Outputs (1)

58 1

3 hits Apply

68 3

3 hits Apply

70.0 °C 3

3 hits Apply

0.0 °C 3

3 hits Apply

100 CLBS, 3000 GATES 3

3 hits Apply

PLASTIC/EPOXY 3

3 hits Apply

QCCJ 3

3 hits Apply

LDCC68,1.0SQ 3

3 hits Apply

Package Shape (1)

SQUARE 3

3 hits Apply

CHIP CARRIER 3

3 hits Apply

Obsolete 3

3 hits Apply

Programmable Logic Type (1)

FIELD PROGRAMMABLE GATE ARRAY 3

3 hits Apply

Not Qualified 3

3 hits Apply

No 1

3 hits Apply

4.699 mm 3

3 hits Apply

5.25 V 3

3 hits Apply

4.75 V 3

3 hits Apply

Supply Voltage-Nom (1)

5 V 3

3 hits Apply

YES 3

3 hits Apply

CMOS 3

3 hits Apply

Temperature Grade (1)

COMMERCIAL 3

3 hits Apply

TIN LEAD 2

3 hits Apply

J BEND 3

3 hits Apply