Parametric results for: XC2018-50PC68C under Field Programmable Gate Arrays

All Filters Additional Feature Clock Frequency-Max Combinatorial Delay of a CLB-Max JESD-30 Code JESD-609 Code Length Manufacturer Moisture Sensitivity Level Number of CLBs Number of Equivalent Gates Number of Inputs Number of Logic Cells Number of Outputs Number of Terminals Operating Temperature-Max Operating Temperature-Min Organization Package Body Material Package Code Package Equivalence Code Package Shape Package Style Part Life Cycle Code Programmable Logic Type Qualification Status Rohs Code Seated Height-Max Supply Voltage-Max Supply Voltage-Min Supply Voltage-Nom Surface Mount Technology Temperature Grade Terminal Finish Terminal Form

MAX. 74 I/OS; 174 FLIP-FLOPS; TYP. GATES = 1000 - 1500 1

1 hit Apply

50 MHz 1

1 hit Apply

Combinatorial Delay of a CLB-Max (1)

15 ns 1

1 hit Apply

S-PQCC-J68 1

1 hit Apply

e0 1

1 hit Apply

24.2316 mm 1

1 hit Apply

Manufacturer (1)

AMD Xilinx 1

1 hit Apply

1 1

1 hit Apply

Number of CLBs (1)

100 1

1 hit Apply

Number of Equivalent Gates (1)

1000 1

1 hit Apply

Number of Inputs (1)

58 1

1 hit Apply

Number of Logic Cells (1)

100 1

1 hit Apply

Number of Outputs (1)

58 1

1 hit Apply

68 1

1 hit Apply

70.0 °C 1

1 hit Apply

0.0 °C 1

1 hit Apply

100 CLBS, 1000 GATES 1

1 hit Apply

PLASTIC/EPOXY 1

1 hit Apply

QCCJ 1

1 hit Apply

LDCC68,1.0SQ 1

1 hit Apply

Package Shape (1)

SQUARE 1

1 hit Apply

CHIP CARRIER 1

1 hit Apply

Obsolete 1

1 hit Apply

Programmable Logic Type (1)

FIELD PROGRAMMABLE GATE ARRAY 1

1 hit Apply

Not Qualified 1

1 hit Apply

No 1

1 hit Apply

4.445 mm 1

1 hit Apply

5.25 V 1

1 hit Apply

4.75 V 1

1 hit Apply

Supply Voltage-Nom (1)

5 V 1

1 hit Apply

YES 1

1 hit Apply

CMOS 1

1 hit Apply

Temperature Grade (1)

COMMERCIAL 1

1 hit Apply

TIN LEAD 1

1 hit Apply

J BEND 1

1 hit Apply