Parametric results for: V54C316162VAT12 under DRAMs

All Filters Access Mode Access Time-Max Clock Frequency-Max (fCLK) I/O Type Interleaved Burst Length JESD-30 Code JESD-609 Code Length Manufacturer Memory Density Memory IC Type Memory Width Number of Functions Number of Ports Number of Terminals Number of Words Number of Words Code Operating Mode Operating Temperature-Max Operating Temperature-Min Organization Output Characteristics Package Body Material Package Code Package Equivalence Code Package Shape Package Style Refresh Cycles Supply Voltage-Nom (Vsup) Access Mode (1)

DUAL BANK PAGE BURST 1

1 hit Apply

Access Time-Max (1)

9 ns 1

1 hit Apply

Clock Frequency-Max (fCLK) (1)

83 MHz 1

1 hit Apply

COMMON 1

1 hit Apply

1,2,4,8 1

1 hit Apply

R-PDSO-G50 1

1 hit Apply

e0 1

1 hit Apply

20.95 mm 1

1 hit Apply

Manufacturer (1)

Mosel Vitelic Corporation 1

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Memory Density (1)

16.7772 Mbit 1

1 hit Apply

SYNCHRONOUS DRAM 1

1 hit Apply

Memory Width (1)

16 1

1 hit Apply

1.0 1

1 hit Apply

1 1

1 hit Apply

50 1

1 hit Apply

1.0486 M 1

1 hit Apply

1000000.0 1

1 hit Apply

SYNCHRONOUS 1

1 hit Apply

70.0 °C 1

1 hit Apply

0.0 °C 1

1 hit Apply

Organization (1)

1MX16 1

1 hit Apply

3-STATE 1

1 hit Apply

PLASTIC/EPOXY 1

1 hit Apply

TSOP2 1

1 hit Apply

TSOP50,.46,32 1

1 hit Apply

RECTANGULAR 1

1 hit Apply

SMALL OUTLINE, THIN PROFILE 1

1 hit Apply

Refresh Cycles (1)

4096 1

1 hit Apply

Supply Voltage-Nom (Vsup) (1)

3.3 V 1

1 hit Apply