Parametric results for: THLD12N11B under DRAMs

All Filters Access Mode Access Time-Max Additional Feature Clock Frequency-Max (fCLK) I/O Type JESD-30 Code Manufacturer Memory Density Memory IC Type Memory Width Number of Functions Number of Ports Number of Terminals Number of Words Number of Words Code Operating Mode Operating Temperature-Max Operating Temperature-Min Organization Output Characteristics Package Body Material Package Code Package Equivalence Code Package Shape Package Style Refresh Cycles Supply Voltage-Nom (Vsup) Access Mode (1)

SINGLE BANK PAGE BURST 3

6 hits Apply

Access Time-Max (3)

7 ns 1 7.5 ns 1 8 ns 1

Min (ns) - Max (ns)

6 hits Apply

AUTO/SELF REFRESH 3

6 hits Apply

Clock Frequency-Max (fCLK) (3)

125 MHz 1 133 MHz 1 143 MHz 1

Min (MHz) - Max (MHz)

6 hits Apply

COMMON 3

6 hits Apply

R-XDMA-N200 3

6 hits Apply

Manufacturer (2)

FUJITSU Limited 3 Toshiba America Electronic Components 3

6 hits Apply

Memory Density (1)

1.0737 Gbit 3

6 hits Apply

DDR DRAM MODULE 3

6 hits Apply

Memory Width (1)

64 3

6 hits Apply

1.0 3

6 hits Apply

1 3

6 hits Apply

200 3

6 hits Apply

16.7772 M 3

6 hits Apply

1.6E7 3

6 hits Apply

SYNCHRONOUS 3

6 hits Apply

70.0 °C 3

6 hits Apply

0.0 °C 3

6 hits Apply

Organization (1)

16MX64 3

6 hits Apply

3-STATE 3

6 hits Apply

UNSPECIFIED 3

6 hits Apply

DIMM 3

6 hits Apply

DIMM184 3

6 hits Apply

RECTANGULAR 3

6 hits Apply

MICROELECTRONIC ASSEMBLY 3

6 hits Apply

Refresh Cycles (1)

8192 3

6 hits Apply

Supply Voltage-Nom (Vsup) (1)

2.5 V 3

6 hits Apply