Parametric results for: S54S112W under FF/Latches

All Filters Family JESD-30 Code JESD-609 Code Load Capacitance (CL) Logic IC Type Manufacturer Max Frequency@Nom-Sup Max I(ol) Number of Bits Number of Functions Number of Terminals Operating Temperature-Max Operating Temperature-Min Output Polarity Package Body Material Package Code Package Equivalence Code Package Shape Package Style Propagation Delay (tpd) Supply Voltage-Nom (Vsup) Surface Mount Trigger Type Family (1)

S 2

4 hits Apply

R-CQFP-F16 2 R-XDFP-F16 2

4 hits Apply

e0 4

4 hits Apply

Load Capacitance (CL) (1)

15 pF 2

4 hits Apply

J-K FLIP-FLOP 4

4 hits Apply

Manufacturer (3)

NXP Semiconductors 1 Philips Semiconductors 2 Signetics 1

4 hits Apply

Max Frequency@Nom-Sup (1)

80 MHz 4

4 hits Apply

20 mA 4

4 hits Apply

Number of Bits (1)

2 2

4 hits Apply

Number of Functions (1)

2.0 4

4 hits Apply

16 4

4 hits Apply

125.0 °C 4

4 hits Apply

-55.0 °C 4

4 hits Apply

COMPLEMENTARY 2

4 hits Apply

CERAMIC 2 CERAMIC, METAL-SEALED COFIRED 2

4 hits Apply

Package Code (1)

DFP 4

4 hits Apply

FL16,.3 4

4 hits Apply

RECTANGULAR 4

4 hits Apply

FLATPACK 4

4 hits Apply

Propagation Delay (tpd) (1)

7 ns 2

4 hits Apply

Supply Voltage-Nom (Vsup) (1)

5 V 4

4 hits Apply

Surface Mount (1)

YES 4

4 hits Apply

Trigger Type (1)

NEGATIVE EDGE 4

4 hits Apply