Parametric results for: ICE5LP2K-SWG36ITR50 under Field Programmable Gate Arrays

All Filters Combinatorial Delay of a CLB-Max JESD-30 Code Length Manufacturer Moisture Sensitivity Level Number of CLBs Number of Inputs Number of Logic Cells Number of Outputs Number of Terminals Operating Temperature-Max Operating Temperature-Min Organization Package Body Material Package Code Package Equivalence Code Package Shape Package Style Packing Method Part Life Cycle Code Peak Reflow Temperature (Cel) Programmable Logic Type Seated Height-Max Supply Voltage-Max Supply Voltage-Min Supply Voltage-Nom Surface Mount Technology Terminal Form Combinatorial Delay of a CLB-Max (1)

9 ns 1

1 hit Apply

S-PBGA-B36 1

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2.078 mm 1

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Manufacturer (1)

Lattice Semiconductor Corporation 1

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1 1

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Number of CLBs (1)

256 1

1 hit Apply

Number of Inputs (1)

26 1

1 hit Apply

Number of Logic Cells (1)

2048 1

1 hit Apply

Number of Outputs (1)

26 1

1 hit Apply

36 1

1 hit Apply

100.0 °C 1

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-40.0 °C 1

1 hit Apply

256 CLBS 1

1 hit Apply

PLASTIC/EPOXY 1

1 hit Apply

VFBGA 1

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BGA36,6X6,14 1

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Package Shape (1)

SQUARE 1

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GRID ARRAY, VERY THIN PROFILE, FINE PITCH 1

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TR 1

1 hit Apply

Obsolete 1

1 hit Apply

260 1

1 hit Apply

Programmable Logic Type (1)

FIELD PROGRAMMABLE GATE ARRAY 1

1 hit Apply

491 µm 1

1 hit Apply

1.26 V 1

1 hit Apply

1.14 V 1

1 hit Apply

Supply Voltage-Nom (1)

1.2 V 1

1 hit Apply

YES 1

1 hit Apply

CMOS 1

1 hit Apply

BALL 1

1 hit Apply