Parametric results for: HYMP125U72AP8 under DRAMs

All Filters Access Mode Access Time-Max Additional Feature Clock Frequency-Max (fCLK) I/O Type JESD-30 Code Manufacturer Memory Density Memory IC Type Memory Width Number of Functions Number of Ports Number of Terminals Number of Words Number of Words Code Operating Mode Operating Temperature-Max Operating Temperature-Min Organization Output Characteristics Package Body Material Package Code Package Equivalence Code Package Shape Package Style Refresh Cycles Supply Voltage-Nom (Vsup) Access Mode (1)

DUAL BANK PAGE BURST 4

4 hits Apply

Access Time-Max (4)

400 ps 1 450 ps 1 500 ps 1 600 ps 1

Min (ns) - Max (ns)

4 hits Apply

AUTO/SELF REFRESH 4

4 hits Apply

Clock Frequency-Max (fCLK) (4)

200 MHz 1 266 MHz 1 333 MHz 1 400 MHz 1

Min (MHz) - Max (MHz)

4 hits Apply

COMMON 4

4 hits Apply

R-XDMA-N240 4

4 hits Apply

Manufacturer (1)

SK Hynix Inc 4

4 hits Apply

Memory Density (1)

19.3274 Gbit 4

4 hits Apply

DDR DRAM MODULE 4

4 hits Apply

Memory Width (1)

72 4

4 hits Apply

1.0 4

4 hits Apply

1 4

4 hits Apply

240 4

4 hits Apply

268.4355 M 4

4 hits Apply

2.56E8 4

4 hits Apply

SYNCHRONOUS 4

4 hits Apply

55.0 °C 4

4 hits Apply

0.0 °C 4

4 hits Apply

Organization (1)

256MX72 4

4 hits Apply

3-STATE 4

4 hits Apply

UNSPECIFIED 4

4 hits Apply

DIMM 4

4 hits Apply

DIMM240,40 4

4 hits Apply

RECTANGULAR 4

4 hits Apply

MICROELECTRONIC ASSEMBLY 4

4 hits Apply

Refresh Cycles (1)

8192 4

4 hits Apply

Supply Voltage-Nom (Vsup) (1)

1.8 V 4

4 hits Apply