Parametric results for: EP1810LC68-45 under Programmable Logic Devices

All Filters Additional Feature Clock Frequency-Max In-System Programmable JESD-30 Code JESD-609 Code JTAG BST Length Manufacturer Number of Dedicated Inputs Number of I/O Lines Number of Macro Cells Number of Terminals Operating Temperature-Max Operating Temperature-Min Organization Output Function Package Body Material Package Code Package Equivalence Code Package Shape Package Style Part Life Cycle Code Peak Reflow Temperature (Cel) Programmable Logic Type Propagation Delay Qualification Status Rohs Code Seated Height-Max Supply Voltage-Max Supply Voltage-Min Supply Voltage-Nom Surface Mount Technology Temperature Grade Terminal Finish Terminal Form

48 MACROCELLS; SHARED INPUT/CLOCK 1

1 hit Apply

33.3 MHz 1

1 hit Apply

NO 1

1 hit Apply

S-PQCC-J68 1

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e0 1

1 hit Apply

NO 1

1 hit Apply

24.2316 mm 1

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Manufacturer (1)

Altera Corporation 1

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Number of Dedicated Inputs (1)

12 1

1 hit Apply

Number of I/O Lines (1)

48 1

1 hit Apply

Number of Macro Cells (1)

48 1

1 hit Apply

68 1

1 hit Apply

70.0 °C 1

1 hit Apply

0.0 °C 1

1 hit Apply

12 DEDICATED INPUTS, 48 I/O 1

1 hit Apply

MACROCELL 1

1 hit Apply

PLASTIC/EPOXY 1

1 hit Apply

QCCJ 1

1 hit Apply

LDCC68,1.0SQ 1

1 hit Apply

Package Shape (1)

SQUARE 1

1 hit Apply

CHIP CARRIER 1

1 hit Apply

Obsolete 1

1 hit Apply

220 1

1 hit Apply

Programmable Logic Type (1)

OT PLD 1

1 hit Apply

Propagation Delay (1)

50 ns 1

1 hit Apply

Not Qualified 1

1 hit Apply

No 1

1 hit Apply

5.08 mm 1

1 hit Apply

5.25 V 1

1 hit Apply

4.75 V 1

1 hit Apply

Supply Voltage-Nom (1)

5 V 1

1 hit Apply

YES 1

1 hit Apply

CMOS 1

1 hit Apply

Temperature Grade (1)

COMMERCIAL 1

1 hit Apply

TIN LEAD 1

1 hit Apply

J BEND 1

1 hit Apply