Parametric results for: 74LVC02APW118 under Gates

All Filters Family JESD-30 Code JESD-609 Code Length Load Capacitance (CL) Logic IC Type Manufacturer Max I(ol) Moisture Sensitivity Level Number of Functions Number of Inputs Number of Terminals Operating Temperature-Max Operating Temperature-Min Package Body Material Package Code Package Equivalence Code Package Shape Package Style Prop. Delay@Nom-Sup Propagation Delay (tpd) Schmitt Trigger Supply Voltage-Nom (Vsup) Surface Mount Family (1)

LVC/LCX/Z 2

2 hits Apply

R-PDSO-G14 2

2 hits Apply

e4 2

2 hits Apply

5 mm 2

2 hits Apply

Load Capacitance (CL) (1)

50 pF 2

2 hits Apply

NOR GATE 2

2 hits Apply

Manufacturer (2)

Nexperia 1 NXP Semiconductors 1

2 hits Apply

24 mA 1

2 hits Apply

1 2

2 hits Apply

Number of Functions (1)

4.0 2

2 hits Apply

Number of Inputs (1)

2 2

2 hits Apply

14 2

2 hits Apply

125.0 °C 2

2 hits Apply

-40.0 °C 2

2 hits Apply

PLASTIC/EPOXY 2

2 hits Apply

Package Code (1)

TSSOP 2

2 hits Apply

TSSOP14,.25 1

2 hits Apply

RECTANGULAR 2

2 hits Apply

SMALL OUTLINE, THIN PROFILE, SHRINK PITCH 2

2 hits Apply

Prop. Delay@Nom-Sup (1)

5.5 ns 1

2 hits Apply

Propagation Delay (tpd) (1)

6.5 ns 2

2 hits Apply

Schmitt Trigger (1)

NO 1

2 hits Apply

Supply Voltage-Nom (Vsup) (1)

2.7 V 2

2 hits Apply

Surface Mount (1)

YES 2

2 hits Apply