Parametric results for: 74HC4049PW,118 under Gates

All Filters Additional Feature Family JESD-30 Code JESD-609 Code Length Load Capacitance (CL) Logic IC Type Manufacturer Max I(ol) Moisture Sensitivity Level Number of Functions Number of Inputs Number of Terminals Operating Temperature-Max Operating Temperature-Min Package Body Material Package Code Package Equivalence Code Package Shape Package Style Prop. Delay@Nom-Sup Propagation Delay (tpd) Schmitt Trigger Supply Voltage-Nom (Vsup) Surface Mount

CMOS-TTL LEVEL TRANSLATOR 1

2 hits Apply

Family (1)

HC/UH 2

2 hits Apply

R-PDSO-G16 2

2 hits Apply

e4 1

2 hits Apply

5 mm 2

2 hits Apply

Load Capacitance (CL) (1)

50 pF 2

2 hits Apply

INVERTER 2

2 hits Apply

Manufacturer (2)

Nexperia 1 NXP Semiconductors 1

2 hits Apply

5.2 mA 2

2 hits Apply

1 2

2 hits Apply

Number of Functions (1)

6.0 2

2 hits Apply

Number of Inputs (1)

1 2

2 hits Apply

16 2

2 hits Apply

125.0 °C 2

2 hits Apply

-40.0 °C 2

2 hits Apply

PLASTIC/EPOXY 2

2 hits Apply

Package Code (1)

TSSOP 2

2 hits Apply

TSSOP16,.25 2

2 hits Apply

RECTANGULAR 2

2 hits Apply

SMALL OUTLINE, THIN PROFILE, SHRINK PITCH 2

2 hits Apply

Prop. Delay@Nom-Sup (1)

26 ns 2

2 hits Apply

Propagation Delay (tpd) (2)

26 ns 1 130 ns 1

Min (ns) - Max (ns)

2 hits Apply

Schmitt Trigger (1)

NO 2

2 hits Apply

Supply Voltage-Nom (Vsup) (1)

5 V 2

2 hits Apply

Surface Mount (1)

YES 2

2 hits Apply