Parametric results for: 100350FC under FF/Latches

All Filters Additional Feature Family JESD-30 Code JESD-609 Code Length Load Capacitance (CL) Logic IC Type Manufacturer Number of Bits Number of Functions Number of Terminals Operating Temperature-Max Operating Temperature-Min Output Characteristics Output Polarity Package Body Material Package Code Package Equivalence Code Package Shape Package Style Prop. Delay@Nom-Sup Propagation Delay (tpd) Surface Mount Trigger Type

WITH DUAL LATCH ENABLE 3 WITH DUAL LATCH ENABLE; OPTEMP SPECIFIED AS TC 2

5 hits Apply

Family (1)

100K 5

5 hits Apply

S-GQFP-F24 5

5 hits Apply

e0 4

5 hits Apply

9.398 mm 5

5 hits Apply

Load Capacitance (CL) (1)

3 pF 2

5 hits Apply

D LATCH 5

5 hits Apply

Manufacturer (3)

Fairchild Semiconductor Corporation 1 National Semiconductor Corporation 2 Texas Instruments 2

5 hits Apply

Number of Bits (1)

6 5

5 hits Apply

Number of Functions (1)

1.0 5

5 hits Apply

24 5

5 hits Apply

85.0 °C 5

5 hits Apply

0.0 °C 5

5 hits Apply

Output Characteristics (1)

OPEN-EMITTER 5

5 hits Apply

COMPLEMENTARY 5

5 hits Apply

CERAMIC, GLASS-SEALED 5

5 hits Apply

Package Code (1)

QFF 5

5 hits Apply

QFL24,.4SQ 4

5 hits Apply

SQUARE 5

5 hits Apply

FLATPACK 5

5 hits Apply

Prop. Delay@Nom-Sup (1)

1.3 ns 4

5 hits Apply

Propagation Delay (tpd) (1)

1.85 ns 3

5 hits Apply

Surface Mount (1)

YES 5

5 hits Apply

Trigger Type (1)

LOW LEVEL 5

5 hits Apply