Parametric results for: 100117Y under Gates

All Filters Additional Feature Family JESD-30 Code JESD-609 Code Load Capacitance (CL) Logic IC Type Manufacturer Number of Functions Number of Inputs Number of Terminals Operating Temperature-Max Operating Temperature-Min Output Characteristics Package Body Material Package Code Package Equivalence Code Package Shape Package Style Prop. Delay@Nom-Sup Propagation Delay (tpd) Schmitt Trigger Supply Voltage-Nom (Vsup) Surface Mount

STROBED OUTPUTS 1

3 hits Apply

Family (1)

100K 3

3 hits Apply

S-GQFP-F24 1 S-XQFP-F24 2

3 hits Apply

e0 2

3 hits Apply

Load Capacitance (CL) (1)

3 pF 1

3 hits Apply

OR-AND/OR-AND-INVERT GATE 3

3 hits Apply

Manufacturer (2)

Philips Semiconductors 2 YAGEO Corporation 1

3 hits Apply

Number of Functions (1)

3.0 3

3 hits Apply

Number of Inputs (1)

4 3

3 hits Apply

24 3

3 hits Apply

85.0 °C 3

3 hits Apply

0.0 °C 3

3 hits Apply

Output Characteristics (1)

OPEN-EMITTER 1

3 hits Apply

CERAMIC 2 CERAMIC, GLASS-SEALED 1

3 hits Apply

Package Code (2)

QFF 2 QFP 1

3 hits Apply

QFL24,.4SQ 3

3 hits Apply

SQUARE 3

3 hits Apply

FLATPACK 3

3 hits Apply

Prop. Delay@Nom-Sup (1)

2.4 ns 2

3 hits Apply

Propagation Delay (tpd) (1)

2.4 ns 3

3 hits Apply

Schmitt Trigger (1)

NO 2

3 hits Apply

Supply Voltage-Nom (Vsup) (1)

-4.5 V 3

3 hits Apply

Surface Mount (1)

YES 3

3 hits Apply