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Dual J-K Positive-Edge-Triggered Flip-Flops with Preset and Clear 16-PDIP 0 to 70
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SN7476N3
Texas Instruments
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SN7476N3
Texas Instruments
Dual J-K Positive-Edge-Triggered Flip-Flops with Preset and Clear 16-PDIP 0 to 70
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Pbfree Code | No | |
Rohs Code | No | |
Part Life Cycle Code | Obsolete | |
Ihs Manufacturer | TEXAS INSTRUMENTS INC | |
Part Package Code | DIP | |
Package Description | DIP, DIP16,.3 | |
Pin Count | 16 | |
Reach Compliance Code | not_compliant | |
HTS Code | 8542.39.00.01 | |
Samacsys Manufacturer | Texas Instruments | |
Additional Feature | MASTER SLAVE OPERATION | |
Family | 7476 | |
JESD-30 Code | R-PDIP-T16 | |
Length | 19.305 mm | |
Logic IC Type | J-K FLIP-FLOP | |
Number of Bits | 2 | |
Number of Functions | 2 | |
Number of Terminals | 16 | |
Operating Temperature-Max | 70 °C | |
Operating Temperature-Min | ||
Output Polarity | COMPLEMENTARY | |
Package Body Material | PLASTIC/EPOXY | |
Package Code | DIP | |
Package Equivalence Code | DIP16,.3 | |
Package Shape | RECTANGULAR | |
Package Style | IN-LINE | |
Peak Reflow Temperature (Cel) | NOT SPECIFIED | |
Propagation Delay (tpd) | 40 ns | |
Qualification Status | Not Qualified | |
Seated Height-Max | 5.08 mm | |
Supply Voltage-Max (Vsup) | 5.25 V | |
Supply Voltage-Min (Vsup) | 4.75 V | |
Supply Voltage-Nom (Vsup) | 5 V | |
Surface Mount | NO | |
Technology | TTL | |
Temperature Grade | COMMERCIAL | |
Terminal Form | THROUGH-HOLE | |
Terminal Pitch | 2.54 mm | |
Terminal Position | DUAL | |
Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED | |
Trigger Type | POSITIVE EDGE | |
Width | 7.62 mm | |
fmax-Min | 20 MHz |