Part Details for SN65LVDS100 by Texas Instruments
Overview of SN65LVDS100 by Texas Instruments
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Part Details for SN65LVDS100
SN65LVDS100 CAD Models
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Reference Designs related to SN65LVDS100
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Efficient: LDO-free Power Supply for a 12-bit 500-MSPS ADC Reference Design
The electrical performance of data converters depends on the cleanliness of their supply voltages. Linear regulators (LDOs) are commonly used but have low efficiency and high power loss: which is unsuitable for portable applications.Using a switch mode power supply (SMPS) instead: such as the TPS62231 and TPS62237: is a cost-effective and efficient power supply solution. Such a solution does not degrade the performance of the 12-bit ADS540x family of analog to digital converters (ADCs) and does not waste excessive power. The test report shows the Signal to Noise Ratio (SNR) and Spurious-Free Dynamic Range (SFDR) comparisons between the two power supplies: which demonstrate the same performance.
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PMP9357 Altera® Arria V FPGA 电源
The PMP9357 reference design is a complete power solution for Altera's Arria V series FPGAs. This design uses several TPS54620 synchronous step down converters, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA. To provide correct power sequenc
- TIPD167 用于电力自动化并支持相位补偿的 8 通道多路复用数据采集系统参考设计
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Wideband RF-to-Digital Complex Receiver-Feedback Signal Chain
This is a wideband complex-receiver reference design and evaluation platform that is ideally suited for use as a feedback receiver for transmitter digital predistortion. The EVM signal chain is ideal for high intermediate-frequency (IF) complex-feedback applications and contains a complex demodulator: TI’s LMH6521 dual-channel DVGA and ADS5402 12-bit 800-MSPS dual-channel ADC. By modifying the onboard filter components: the signal chain is configurable for a variety of frequency plans. The EVM also includes TI’s LMK04808 dual-PLL clock jitter cleaner and generator to provide an onboard low-noise clocking solution. The LMH6521 DVGA gain is controlled through the GUI or alternatively through the high speed connector with an FPGA.