Part Details for DS90LV028A by Maxim Integrated Products

This reference design provides the solution for synchronization design challenges associated with emerging 5G adapted applications like massive multiple input multiple output (mMIMO): phase array RADAR and communication payload. The typical RF front end contains antenna: low noise amplifier (LNA): mixer : local oscillator (LO) in analog domain and analog to digital converter: numerical controlled oscillator (NCO) and digital down converter (DDC) in digital domain. To achieve overall system synchronization these digital blocks need to be synchronize with system clock. This reference design uses ADC12DJ3200 data converter: achieve less than 5-ps channel-to-channel skew across multiple receiver with deterministic latency by synchronizing on chip NCO with SYNC~ and uses noiseless aperture delay adjustment (tAD Adjust) feature to further reduce skew. This design also provides a very low phase noise clocking solution based the LMX2594 wide band PLL and the LMK04828 synthesizer and jitter cleaner.

This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate: however: matching individual ADCs offset: gain and sampling time mismatch is critical to achieve performance. The complexity of interleaving increases with higher sampling clock. The phase matching between the ADCs is one of the critical specifications to achieve better SFDR and ENOB. This reference design uses the noiseless aperture delay adjustment feature on ADC12DJ5200RF with a 19 fs precise phase control steps that eases 20.8 GSPS interleaving implementation. The reference design uses on-board low noise JESD204B clock generator based on LMK04828 and LMX2594 that meets 12 bit system performance requirement.

High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR: SFDR: and ENOB. This reference design supports high channel count JESD204B synchronized clocks using one master and multiple slave clocking devices. This design provides multichannel JESD204B clocks using TI’s LMK04828 clock jitter cleaner and LMX2594 wideband PLL with integrated VCOs to achieve clock-to-clock skew of <10 ps. This design is tested with TI’s ADC12DJ3200 EVMs at 3 GSPS: and a channel-to-channel skew of < 50 ps is achieved with improved SNR performance. All key design theories are described to guide users through the part selection process and design optimization. Finally: schematics: board layouts: hardware testing: and test results are included.

This reference design demonstrates an efficient: low noise 5-rail power-supply design for very high-speed DAQ systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency synchronized and phase-shifted in order to minimize input current ripple and control frequency content. Furthermore: any potential radiated electromagnetic interference (EMI) is minimized by using high performance HotRodTM packaging technology.

This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation: which affects overall system SNR: SFDR: channel to channel skew and deterministic latency. This reference design demonstrates multi-channel AFE and clock solution using high speed data converters with JESD204B: high speed amplifiers: high performance clocks and low noise power solutions to achieve optimum system performance

This reference design: an 8-channel analog front end (AFE): is demonstrated using two AFE7444 4-channel RF transceivers and a LMK04828-LMX2594 based clocking subsystem which can enable designs to scale to 16 or more channels. Each AFE channel consists of a 14-bit: 9-GSPS DAC and a 3-GSPS ADC that is synchronized to less than 10ps skew with > 75-dB dynamic range at 2.6 GHz.

High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR: SFDR: and ENOB. This reference design supports scaling up JESD204B synchronized clocks in daisy chain configuration. This design provides multichannel JESD204B clocks using TI’s LMK04828 clock jitter cleaner and LMX2594 wideband PLL with integrated VCOs to achieve clock-to-clock skew of <10 ps. This design is tested with TI’s ADC12DJ3200 EVMs at 3 GSPS: and a channel-to-channel skew of < 50 ps is achieved with improved SNR performance. All key design theories are described to guide users through the part selection process and design optimization. Finally: schematics: board layouts: hardware testing: and test results are included.