Part Details for ICE5LP2K-SWG36ITR50 by Lattice Semiconductor Corporation
Overview of ICE5LP2K-SWG36ITR50 by Lattice Semiconductor Corporation
- Distributor Offerings: (1 listing)
- Number of FFF Equivalents: (0 replacements)
- CAD Models: (Request Part)
- Number of Functional Equivalents: (0 options)
- Part Data Attributes: (Available)
- Reference Designs: (Not Available)
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Price & Stock for ICE5LP2K-SWG36ITR50
| Part # | Distributor | Description | Stock | Price | Buy | |
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DISTI #
220-1928-1-ND
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DigiKey | IC FPGA 26 I/O 36WLCSP Min Qty: 1 Lead time: 16 Weeks Container: Cut Tape (CT), Digi-Reel®, Tape & Reel (TR) |
1 In Stock |
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$4.2500 | Buy Now |
Part Details for ICE5LP2K-SWG36ITR50
ICE5LP2K-SWG36ITR50 CAD Models
ICE5LP2K-SWG36ITR50 Part Data Attributes
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ICE5LP2K-SWG36ITR50
Lattice Semiconductor Corporation
Buy Now
Datasheet
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ICE5LP2K-SWG36ITR50
Lattice Semiconductor Corporation
Field Programmable Gate Array,
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| Part Life Cycle Code | Obsolete | |
| Ihs Manufacturer | LATTICE SEMICONDUCTOR CORP | |
| Package Description | , | |
| Reach Compliance Code | compliant | |
| ECCN Code | EAR99 | |
| HTS Code | 8542.39.00.01 | |
| Combinatorial Delay of a CLB-Max | 9 ns | |
| JESD-30 Code | S-PBGA-B36 | |
| Length | 2.078 mm | |
| Moisture Sensitivity Level | 1 | |
| Number of CLBs | 256 | |
| Number of Inputs | 26 | |
| Number of Logic Cells | 2048 | |
| Number of Outputs | 26 | |
| Number of Terminals | 36 | |
| Operating Temperature-Max | 100 °C | |
| Operating Temperature-Min | -40 °C | |
| Organization | 256 CLBS | |
| Package Body Material | PLASTIC/EPOXY | |
| Package Code | VFBGA | |
| Package Equivalence Code | BGA36,6X6,14 | |
| Package Shape | SQUARE | |
| Package Style | GRID ARRAY, VERY THIN PROFILE, FINE PITCH | |
| Packing Method | TR | |
| Peak Reflow Temperature (Cel) | 260 | |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY | |
| Seated Height-Max | 0.491 mm | |
| Supply Voltage-Max | 1.26 V | |
| Supply Voltage-Min | 1.14 V | |
| Supply Voltage-Nom | 1.2 V | |
| Surface Mount | YES | |
| Technology | CMOS | |
| Terminal Form | BALL | |
| Terminal Pitch | 0.35 mm | |
| Terminal Position | BOTTOM | |
| Time@Peak Reflow Temperature-Max (s) | 30 | |
| Width | 2.078 mm |