KAD5512HP-17Q72 vs KAD5512HP-12Q72 feature comparison

KAD5512HP-17Q72 Intersil Corporation

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KAD5512HP-12Q72 Intersil Corporation

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Part Life Cycle Code Transferred Transferred
Ihs Manufacturer INTERSIL CORP INTERSIL CORP
Part Package Code QFN, QFN QFN, QFN
Package Description HVQCCN, LCC72,.39SQ,20 HVQCCN, LCC72,.39SQ,20
Pin Count 48, 72 48, 72
Reach Compliance Code compliant compliant
ECCN Code 3A991.C.2 3A991.C.2
HTS Code 8542.39.00.01 8542.39.00.01
Factory Lead Time 26 Weeks 26 Weeks
Analog Input Voltage-Max 1.54 V 1.54 V
Analog Input Voltage-Min
Conversion Time-Max 0.0059 µs 0.008 µs
Converter Type ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD
JESD-30 Code S-PQCC-N72 S-PQCC-N72
JESD-609 Code e4 e4
Length 10 mm 10 mm
Linearity Error-Max (EL) 0.0488% 0.061%
Moisture Sensitivity Level 3 3
Number of Analog In Channels 1 1
Number of Bits 12 12
Number of Functions 1 1
Number of Terminals 72 72
Operating Temperature-Max 85 °C 85 °C
Operating Temperature-Min -40 °C -40 °C
Output Bit Code OFFSET BINARY, 2'S COMPLEMENT BINARY, GRAY CODE OFFSET BINARY, 2'S COMPLEMENT BINARY, GRAY CODE
Output Format PARALLEL, WORD PARALLEL, WORD
Package Body Material PLASTIC/EPOXY PLASTIC/EPOXY
Package Code HVQCCN HVQCCN
Package Equivalence Code LCC72,.39SQ,20 LCC72,.39SQ,20
Package Shape SQUARE SQUARE
Package Style CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Cel) 260 260
Qualification Status Not Qualified Not Qualified
Sample Rate 170 MHz 125 MHz
Sample and Hold / Track and Hold SAMPLE SAMPLE
Seated Height-Max 0.9 mm 0.9 mm
Supply Voltage-Nom 1.8 V 1.8 V
Surface Mount YES YES
Technology CMOS CMOS
Temperature Grade INDUSTRIAL INDUSTRIAL
Terminal Finish NICKEL PALLADIUM GOLD NICKEL PALLADIUM GOLD
Terminal Form NO LEAD NO LEAD
Terminal Pitch 0.5 mm 0.5 mm
Terminal Position QUAD QUAD
Time@Peak Reflow Temperature-Max (s) 30 30
Width 10 mm 10 mm
Base Number Matches 1 1

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