Findchips: Compare EP610DC-15 vs GAL20V8A-12LJC

EP610DC-15 vs GAL20V8A-12LJC feature comparison

Buy Now Datasheet

Buy Now Datasheet

Pbfree Code	No	No
Rohs Code	No	No
Part Life Cycle Code	Obsolete	Obsolete
Ihs Manufacturer	ALTERA CORP	NATIONAL SEMICONDUCTOR CORP
Part Package Code	DIP	DIP
Package Description	WINDOWED, CERDIP-24	DIP, DIP24,.3
Pin Count	24	24
Reach Compliance Code	unknown	unknown
HTS Code	8542.39.00.01	8542.39.00.01
Architecture	PAL-TYPE	PAL-TYPE
Clock Frequency-Max	71.4 MHz	48 MHz
JESD-30 Code	R-GDIP-T24	R-GDIP-T24
JESD-609 Code	e0	e0
Number of Dedicated Inputs	4	12
Number of I/O Lines	16	8
Number of Inputs	20	20
Number of Outputs	16	8
Number of Product Terms	160	64
Number of Terminals	24	24
Operating Temperature-Max	70 °C	75 °C
Operating Temperature-Min
Organization	4 DEDICATED INPUTS, 16 I/O	12 DEDICATED INPUTS, 8 I/O
Output Function	MACROCELL	MACROCELL
Package Body Material	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED
Package Code	DIP	DIP
Package Equivalence Code	DIP24,.3	DIP24,.3
Package Shape	RECTANGULAR	RECTANGULAR
Package Style	IN-LINE	IN-LINE
Peak Reflow Temperature (Cel)	220
Programmable Logic Type	UV PLD	EE PLD
Propagation Delay	17 ns	12 ns
Qualification Status	Not Qualified	Not Qualified
Supply Voltage-Max	5.25 V	5.25 V
Supply Voltage-Min	4.75 V	4.75 V
Supply Voltage-Nom	5 V	5 V
Surface Mount	NO	NO
Technology	CMOS	CMOS
Temperature Grade	COMMERCIAL	COMMERCIAL EXTENDED
Terminal Finish	TIN LEAD	TIN LEAD
Terminal Form	THROUGH-HOLE	THROUGH-HOLE
Terminal Pitch	2.54 mm	2.54 mm
Terminal Position	DUAL	DUAL
Base Number Matches	1	2
Seated Height-Max		5.715 mm
Width		7.62 mm
	Programmable Logic » Programmable Logic Devices	Programmable Logic » Programmable Logic Devices