EP2S30F672C3N vs EP2S30F672C5 feature comparison

EP2S30F672C3N Altera Corporation

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EP2S30F672C5 Intel Corporation

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Pbfree Code Yes
Rohs Code Yes No
Part Life Cycle Code Transferred Obsolete
Ihs Manufacturer ALTERA CORP INTEL CORP
Part Package Code BGA
Package Description 35 X 35 MM, 1 MM PITCH, FBGA-672 35 X 35 MM, 1 MM PITCH, FBGA-672
Pin Count 672
Reach Compliance Code unknown compliant
HTS Code 8542.39.00.01 8542.39.00.01
Samacsys Manufacturer Intel
Clock Frequency-Max 717 MHz 640 MHz
Combinatorial Delay of a CLB-Max 4.45 ns 5.962 ns
JESD-30 Code S-PBGA-B672 S-PBGA-B672
JESD-609 Code e1 e0
Length 35 mm 35 mm
Moisture Sensitivity Level 3 3
Number of CLBs 13552 13552
Number of Inputs 500 500
Number of Logic Cells 33880 33880
Number of Outputs 492 492
Number of Terminals 672 672
Operating Temperature-Max 85 °C 85 °C
Operating Temperature-Min
Organization 13552 CLBS 13552 CLBS
Package Body Material PLASTIC/EPOXY PLASTIC/EPOXY
Package Code BGA BGA
Package Equivalence Code BGA672,26X26,40 BGA672,26X26,40
Package Shape SQUARE SQUARE
Package Style GRID ARRAY GRID ARRAY
Peak Reflow Temperature (Cel) 245
Programmable Logic Type FIELD PROGRAMMABLE GATE ARRAY FIELD PROGRAMMABLE GATE ARRAY
Qualification Status Not Qualified Not Qualified
Seated Height-Max 2.6 mm 2.6 mm
Supply Voltage-Max 1.25 V 1.25 V
Supply Voltage-Min 1.15 V 1.15 V
Supply Voltage-Nom 1.2 V 1.2 V
Surface Mount YES YES
Technology CMOS CMOS
Temperature Grade OTHER OTHER
Terminal Finish TIN SILVER COPPER TIN LEAD
Terminal Form BALL BALL
Terminal Pitch 1.27 mm 1.27 mm
Terminal Position BOTTOM BOTTOM
Time@Peak Reflow Temperature-Max (s) 30
Width 35 mm 35 mm
Base Number Matches 1 2

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