EP2S30F672C5
vs
EP2S30F672C4
feature comparison
| Rohs Code |
No
|
No
|
| Part Life Cycle Code |
Obsolete
|
Transferred
|
| Ihs Manufacturer |
INTEL CORP
|
ALTERA CORP
|
| Package Description |
35 X 35 MM, 1 MM PITCH, FBGA-672
|
35 X 35 MM, 1 MM PITCH, FBGA-672
|
| Reach Compliance Code |
compliant
|
not_compliant
|
| HTS Code |
8542.39.00.01
|
8542.39.00.01
|
| Clock Frequency-Max |
640 MHz
|
717 MHz
|
| Combinatorial Delay of a CLB-Max |
5.962 ns
|
5.117 ns
|
| JESD-30 Code |
S-PBGA-B672
|
S-PBGA-B672
|
| JESD-609 Code |
e0
|
e0
|
| Length |
35 mm
|
35 mm
|
| Moisture Sensitivity Level |
3
|
3
|
| Number of CLBs |
13552
|
13552
|
| Number of Inputs |
500
|
500
|
| Number of Logic Cells |
33880
|
33880
|
| Number of Outputs |
492
|
492
|
| Number of Terminals |
672
|
672
|
| Operating Temperature-Max |
85 °C
|
85 °C
|
| Operating Temperature-Min |
|
|
| Organization |
13552 CLBS
|
13552 CLBS
|
| Package Body Material |
PLASTIC/EPOXY
|
PLASTIC/EPOXY
|
| Package Code |
BGA
|
BGA
|
| Package Equivalence Code |
BGA672,26X26,40
|
BGA672,26X26,40
|
| Package Shape |
SQUARE
|
SQUARE
|
| Package Style |
GRID ARRAY
|
GRID ARRAY
|
| Programmable Logic Type |
FIELD PROGRAMMABLE GATE ARRAY
|
FIELD PROGRAMMABLE GATE ARRAY
|
| Qualification Status |
Not Qualified
|
Not Qualified
|
| Seated Height-Max |
2.6 mm
|
2.6 mm
|
| Supply Voltage-Max |
1.25 V
|
1.25 V
|
| Supply Voltage-Min |
1.15 V
|
1.15 V
|
| Supply Voltage-Nom |
1.2 V
|
1.2 V
|
| Surface Mount |
YES
|
YES
|
| Technology |
CMOS
|
CMOS
|
| Temperature Grade |
OTHER
|
OTHER
|
| Terminal Finish |
TIN LEAD
|
TIN LEAD
|
| Terminal Form |
BALL
|
BALL
|
| Terminal Pitch |
1.27 mm
|
1.27 mm
|
| Terminal Position |
BOTTOM
|
BOTTOM
|
| Width |
35 mm
|
35 mm
|
| Base Number Matches |
2
|
2
|
| Pbfree Code |
|
No
|
| Part Package Code |
|
BGA
|
| Pin Count |
|
672
|
| Peak Reflow Temperature (Cel) |
|
220
|
| Time@Peak Reflow Temperature-Max (s) |
|
20
|
|
|
|
Compare EP2S30F672C5 with alternatives
Compare EP2S30F672C4 with alternatives