CY7C346B-30RI vs CY7C373-83JI feature comparison

CY7C346B-30RI Teledyne e2v

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CY7C373-83JI Cypress Semiconductor

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Part Life Cycle Code Active Obsolete
Ihs Manufacturer E2V TECHNOLOGIES PLC CYPRESS SEMICONDUCTOR CORP
Package Description , PLASTIC, LCC-84
Reach Compliance Code compliant not_compliant
HTS Code 8542.39.00.01 8542.39.00.01
Architecture PLA-TYPE
Clock Frequency-Max 27.7 MHz 62.5 MHz
In-System Programmable NO NO
JESD-30 Code S-CPGA-P100 S-PQCC-J84
JTAG BST NO NO
Length 33.34 mm 29.3116 mm
Number of Dedicated Inputs 19 2
Number of I/O Lines 64 64
Number of Inputs 84
Number of Macro Cells 128 64
Number of Outputs 64
Number of Product Terms 256
Number of Terminals 100 84
Operating Temperature-Max 85 °C 85 °C
Operating Temperature-Min -40 °C -40 °C
Organization 19 DEDICATED INPUTS, 64 I/O 2 DEDICATED INPUTS, 64 I/O
Output Function MACROCELL MACROCELL
Package Body Material CERAMIC, METAL-SEALED COFIRED PLASTIC/EPOXY
Package Code WPGA QCCJ
Package Equivalence Code PGA100M,13X13 LDCC84,1.2SQ
Package Shape SQUARE SQUARE
Package Style GRID ARRAY, WINDOW CHIP CARRIER
Programmable Logic Type UV PLD FLASH PLD
Propagation Delay 59 ns 19 ns
Seated Height-Max 5.207 mm 5.08 mm
Supply Voltage-Max 5.5 V 5.5 V
Supply Voltage-Min 4.5 V 4.5 V
Supply Voltage-Nom 5 V 5 V
Surface Mount YES YES
Technology CMOS CMOS
Terminal Form PIN/PEG J BEND
Terminal Pitch 2.54 mm 1.27 mm
Terminal Position PERPENDICULAR QUAD
Width 33.34 mm 29.3116 mm
Base Number Matches 2 1
Rohs Code No
Part Package Code LCC
Pin Count 84
Additional Feature LABS INTERCONNECTED BY PIA; 4 LABS; 64 MACROCELLS; 4 EXTERNAL CLOCKS; SHARED INPUT/CLOCK
JESD-609 Code e0
Qualification Status Not Qualified
Temperature Grade INDUSTRIAL
Terminal Finish TIN LEAD

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