7140SA25JGB
vs
IDT7140LA25CG
feature comparison
All Stats
Differences Only
Pbfree Code
Rohs Code
Part Life Cycle Code
Transferred
Transferred
Ihs Manufacturer
INTEGRATED DEVICE TECHNOLOGY INC
INTEGRATED DEVICE TECHNOLOGY INC
Part Package Code
LCC
DIP
Package Description
QCCJ, LDCC52,.8SQ
DIP, DIP48,.6
Pin Count
52
48
Reach Compliance Code
compliant
compliant
ECCN Code
3A001.A.2.C
EAR99
HTS Code
8542.32.00.41
8542.32.00.41
Access Time-Max
25 ns
25 ns
I/O Type
COMMON
COMMON
JESD-30 Code
S-PQCC-J52
R-CDIP-T48
JESD-609 Code
e3
e3
Length
19.1262 mm
60.96 mm
Memory Density
8192 bit
8192 bit
Memory IC Type
MULTI-PORT SRAM
MULTI-PORT SRAM
Memory Width
8
8
Moisture Sensitivity Level
1
Number of Functions
1
1
Number of Ports
2
2
Number of Terminals
52
48
Number of Words
1024 words
1024 words
Number of Words Code
1000
1000
Operating Mode
ASYNCHRONOUS
ASYNCHRONOUS
Operating Temperature-Max
125 °C
70 °C
Operating Temperature-Min
-55 °C
Organization
1KX8
1KX8
Output Characteristics
3-STATE
3-STATE
Package Body Material
PLASTIC/EPOXY
CERAMIC, METAL-SEALED COFIRED
Package Code
QCCJ
DIP
Package Equivalence Code
LDCC52,.8SQ
DIP48,.6
Package Shape
SQUARE
RECTANGULAR
Package Style
CHIP CARRIER
IN-LINE
Parallel/Serial
PARALLEL
PARALLEL
Peak Reflow Temperature (Cel)
260
Qualification Status
Not Qualified
Not Qualified
Screening Level
MIL-PRF-38535 Class Q
Seated Height-Max
4.572 mm
4.826 mm
Standby Current-Max
0.03 A
0.0015 A
Standby Voltage-Min
4.5 V
2 V
Supply Current-Max
0.28 mA
0.17 mA
Supply Voltage-Max (Vsup)
5.5 V
5.5 V
Supply Voltage-Min (Vsup)
4.5 V
4.5 V
Supply Voltage-Nom (Vsup)
5 V
5 V
Surface Mount
YES
NO
Technology
CMOS
CMOS
Temperature Grade
MILITARY
COMMERCIAL
Terminal Finish
Matte Tin (Sn) - annealed
MATTE TIN
Terminal Form
J BEND
THROUGH-HOLE
Terminal Pitch
1.27 mm
2.54 mm
Terminal Position
QUAD
DUAL
Time@Peak Reflow Temperature-Max (s)
30
Width
19.1262 mm
15.24 mm
Base Number Matches
4
5
Compare 7140SA25JGB with alternatives
Compare IDT7140LA25CG with alternatives