Parametric results for: xc2s50-5pqg208c under Field Programmable Gate Arrays

All Filters Additional Feature Clock Frequency-Max Combinatorial Delay of a CLB-Max JESD-30 Code JESD-609 Code Length Manufacturer Moisture Sensitivity Level Number of CLBs Number of Equivalent Gates Number of Inputs Number of Logic Cells Number of Outputs Number of Terminals Operating Temperature-Max Operating Temperature-Min Organization Package Body Material Package Code Package Equivalence Code Package Shape Package Style Part Life Cycle Code Pbfree Code Peak Reflow Temperature (Cel) Programmable Logic Type Qualification Status Rohs Code Seated Height-Max Supply Voltage-Max Supply Voltage-Min Supply Voltage-Nom Surface Mount Temperature Grade Terminal Finish Terminal Form

MAXIMUM USABLE GATES 50000 1

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263 MHz 1

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Combinatorial Delay of a CLB-Max (1)

700 ps 1

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S-PQFP-G208 1

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e3 1

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28 mm 1

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Manufacturer (1)

AMD Xilinx 1

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3 1

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Number of CLBs (1)

384 1

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Number of Equivalent Gates (1)

50000 1

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Number of Inputs (1)

176 1

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Number of Logic Cells (1)

1728 1

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Number of Outputs (1)

176 1

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208 1

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85.0 °C 1

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0.0 °C 1

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384 CLBS, 50000 GATES 1

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PLASTIC/EPOXY 1

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FQFP 1

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QFP208,1.2SQ,20 1

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Package Shape (1)

SQUARE 1

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FLATPACK, FINE PITCH 1

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Obsolete 1

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Yes 1

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245 1

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Programmable Logic Type (1)

FIELD PROGRAMMABLE GATE ARRAY 1

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Not Qualified 1

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Yes 1

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4.1 mm 1

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2.625 V 1

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2.375 V 1

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Supply Voltage-Nom (1)

2.5 V 1

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YES 1

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Temperature Grade (1)

OTHER 1

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Matte Tin (Sn) 1

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GULL WING 1

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