Parametric results for: XC7A200T-L1SBG484I under Field Programmable Gate Arrays

All Filters Combinatorial Delay of a CLB-Max JESD-30 Code JESD-609 Code Length Manufacturer Moisture Sensitivity Level Number of CLBs Number of Inputs Number of Logic Cells Number of Outputs Number of Terminals Operating Temperature-Max Operating Temperature-Min Organization Package Body Material Package Code Package Shape Package Style Part Life Cycle Code Peak Reflow Temperature (Cel) Programmable Logic Type Rohs Code Seated Height-Max Supply Voltage-Max Supply Voltage-Min Supply Voltage-Nom Surface Mount Terminal Finish Terminal Form Combinatorial Delay of a CLB-Max (1)

1.27 ns 1

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S-PBGA-B484 1

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e1 1

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19 mm 1

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Manufacturer (1)

AMD Xilinx 1

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4 1

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Number of CLBs (1)

16825 1

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Number of Inputs (1)

285 1

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Number of Logic Cells (1)

215360 1

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Number of Outputs (1)

285 1

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484 1

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100.0 °C 1

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-40.0 °C 1

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16825 CLBS 1

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PLASTIC/EPOXY 1

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FBGA 1

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Package Shape (1)

SQUARE 1

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GRID ARRAY, FINE PITCH 1

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Transferred 1

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250 1

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Programmable Logic Type (1)

FIELD PROGRAMMABLE GATE ARRAY 1

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Yes 1

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2.44 mm 1

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980 mV 1

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920 mV 1

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Supply Voltage-Nom (1)

950 mV 1

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YES 1

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TIN SILVER COPPER 1

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BALL 1

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