Part Details for TPS51116 by Texas Instruments
Overview of TPS51116 by Texas Instruments
- Distributor Offerings: (1 listing)
- Number of FFF Equivalents: (0 crosses)
- CAD Models: (Request Part)
- Number of Functional Equivalents: (0 crosses)
- Part Data Attributes: (Not Available)
- Reference Designs: (Available)
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Price & Stock for TPS51116
| Part # | Distributor | Description | Stock | Price | Buy | |
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Chip1Cloud | COMPLETE DDR AND DDR2 MEMORY POWER SOLUTION SYNCHRONOUS BUCK CONTROLLER, 3-A LDO, BUFFERED REFERENCE | 2341 |
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RFQ |
Part Details for TPS51116
TPS51116 CAD Models
Resources and Additional Insights for TPS51116
Reference Designs related to TPS51116
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PMP9656 48V-60VDC 输入、12V/250W 有源钳位正向参考设计
This reference design generates a 12V/21A output from 54V DC input. The UCC2897A controls an active clamp forward converter power stage. The low gate charge and low RDSon of the CSD18532Q5B, implemented as self-driven synchronous rectifiers, allow this design to achieve a max load efficiency of n
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DM365DVR-UD1 DM365 数码摄像机参考设计
A DVR reference design based on the TMS320DM365 digital media processor with DaVinci technology and the TI TVP5158 multi-channel video decoder for faster development at a reduced cost.
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Complete Power Solution for DDR or DDR2 Memory Applications
This DDR reference design provides a VDDQ of 2.5V @ 6A and a VTT of 1.25V. The 2.5V sync buck converter achieves an efficiency of 92% while the 1.25V minimizes area by implementing a built-in LDO and has excellent tracking performance.
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TIDA-01402 用于缓冲 DAC 信号的高精度参考设计
此参考设计是业界首款零交叉和零漂移放大器 (OPA388)，用于缓冲数模转换器 (DAC) 的模拟输出。它展示了零交叉和零漂移功能的重要性，以及它们如何最大程度地减小系统的积分非线性 (INL) 以及如何使用 DAC (DAC8830) 的满标量程。
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PMP10338 100V-400Vdc 输入、15V/25mA 辅助电源参考设计
This reference design generates a non-isolated 15V/25mA output from a 100V-400V DC input. It is intended to be used as an auxillary bias supply in off-line applications. It can be connected directly to the bulk input cap, after the bridge rectifier in most AC/DC system. The UCC28910 w
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Altera Cyclone III FPGA Power Management Reference Design
The Cyclone III power management design is a complete: non-isolated power solution and provides all 5 required rails for powering the FPGA. The design also includes complete power solutions for DDR Memory VTT and VDDQ rails and USB power. This design is optimized to power the Altera 3C25F324 starter kit.
- Sync Buck: Linear Regulator (1.5V @ 9A: 0.75V @ 3A)
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Single Chip DDR3 Supply using the TPS51116
PMP3130 uses the TPS51116 to generate a DDR3 supply for VDDQ and VTT. The VDDQ supply is generated from single cell lithium ion battery to 1.5V at 4A using a synchronous buck converter. The VTT supply is generated using a LDO from 1.5V to 0.75V at up to 3A load current. The TPS51116 is designed to operate in low power skip mode to keep light load efficiency high for portable applications.
1 - 5 of 8 reference designs