Part Details for OR3T807BC432-DB by Lattice Semiconductor Corporation
Overview of OR3T807BC432-DB by Lattice Semiconductor Corporation
- Distributor Offerings: (2 listings)
- Number of FFF Equivalents: (0 crosses)
- CAD Models: (Request Part)
- Number of Functional Equivalents: (0 crosses)
- Part Data Attributes: (Available)
- Reference Designs: (Not Available)
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Applications
Computing and Data Storage
Price & Stock for OR3T807BC432-DB
Part # | Distributor | Description | Stock | Price | Buy | |
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DISTI #
2156-OR3T807BC432-DB-ND
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DigiKey | FPGA, 484 CLBS, 116000 GATES Min Qty: 2 Lead time: 1 Weeks Container: Bulk MARKETPLACE PRODUCT |
145 In Stock |
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$161.4200 | Buy Now |
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Rochester Electronics | Field Programmable Gate Array, 484 CLBs, 116000 Gates, 3872-Cell PBGA432 RoHS: Not Compliant Status: Obsolete Min Qty: 1 | 145 |
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$138.5300 / $162.9700 | Buy Now |
Part Details for OR3T807BC432-DB
OR3T807BC432-DB CAD Models
OR3T807BC432-DB Part Data Attributes
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OR3T807BC432-DB
Lattice Semiconductor Corporation
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Datasheet
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OR3T807BC432-DB
Lattice Semiconductor Corporation
Field Programmable Gate Array, 484 CLBs, 116000 Gates, 3872-Cell, CMOS, PBGA432, PLASTIC, EBGA-432
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Rohs Code | No | |
Part Life Cycle Code | Obsolete | |
Ihs Manufacturer | LATTICE SEMICONDUCTOR CORP | |
Part Package Code | BGA | |
Package Description | LBGA, BGA432,31X31,50 | |
Pin Count | 432 | |
Reach Compliance Code | not_compliant | |
HTS Code | 8542.39.00.01 | |
Combinatorial Delay of a CLB-Max | 1.05 ns | |
JESD-30 Code | S-PBGA-B432 | |
JESD-609 Code | e0 | |
Length | 40 mm | |
Moisture Sensitivity Level | 3 | |
Number of CLBs | 484 | |
Number of Equivalent Gates | 116000 | |
Number of Inputs | 338 | |
Number of Logic Cells | 3872 | |
Number of Outputs | 338 | |
Number of Terminals | 432 | |
Operating Temperature-Max | 70 °C | |
Operating Temperature-Min | ||
Organization | 484 CLBS, 116000 GATES | |
Package Body Material | PLASTIC/EPOXY | |
Package Code | LBGA | |
Package Equivalence Code | BGA432,31X31,50 | |
Package Shape | SQUARE | |
Package Style | GRID ARRAY, LOW PROFILE | |
Peak Reflow Temperature (Cel) | 225 | |
Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY | |
Qualification Status | Not Qualified | |
Seated Height-Max | 1.67 mm | |
Supply Voltage-Max | 3.6 V | |
Supply Voltage-Min | 3 V | |
Supply Voltage-Nom | 3.3 V | |
Surface Mount | YES | |
Technology | CMOS | |
Temperature Grade | COMMERCIAL | |
Terminal Finish | Tin/Lead (Sn/Pb) | |
Terminal Form | BALL | |
Terminal Pitch | 1.27 mm | |
Terminal Position | BOTTOM | |
Time@Peak Reflow Temperature-Max (s) | 30 | |
Width | 40 mm |