Part Details for LMZ14 by National Semiconductor Corporation
Overview of LMZ14 by National Semiconductor Corporation
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Part Details for LMZ14
LMZ14 CAD Models
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Reference Designs related to LMZ14
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TIDM-TM4C129POEAUDIO 以太网供电 (PoE) 音频通信参考设计
本设计使用具有集成以太网 PHY 的德州仪器 (TI) 高性能 TM4C129x 微处理器 (MCU) 借助网络提供的电源（PoE 解决方案）而非单独的外部电源来高效捕获、交换和回放音频。该应用使用 TivaWare 图形库来实现用户界面，使用户界面具有触控、具有通过网络交换数据的 lwIP，以及通过压缩音频数据来改善带宽利用的 Opus Audio Codec。
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PMP8762 用于消费类电子产品的低线路、宽输入范围 LLC 谐振式转换器 (12V/10A)
PMP8762 参考设计使用单 LLC 谐振转换器级通过低线路输入电压（100Vac 至 132Vac）提供 12V/10A 输出。该设计的特点是电路成本低、电磁干扰（感应和辐射）小且效率高（满负荷时超过 87%）。该设计使用 UCC25600 谐振转换器控制器及 UCC27702 高侧闸极驱动器来控制 LLC 谐振转换器。
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Non-isolated power architecture with diagnostics reference design for protection relay modules
This reference design showcases non-isolated power supply architectures for protection relays with analog input/output and communication modules generated from 5-: 12-: or 24-V DC input. To generate the power supplies the design uses DC/DC converters with an integrated FET: a power module with an integrated inductor for size- and design-time-constrained applications: a HotRod™ package type for applications requiring low EMI and linear regulators (LDOs) for low ripple. Protections include a flat clamp TVS for input transient protection: an eFuse with configurable load current for overload protection and an ideal diode controller for input reversal protection. Additional features include an auto-switching power MUX: an analog temperature sensor: an input OK indication: a “no load” detection and a voltage supervisor.
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TIDA-01056 用于在最大限度地减小 EMI 的同时优化供电效率的 20 位 1MSPS DAQ 参考设计
该适用于高性能数据采集 (DAQ) 系统的参考设计优化了功率级，以降低功耗并最大程度地减小开关稳压器的 EMI 影响（通过使用 LMS3635-Q1 降压转换器）。与 LM53635 降压转换器相比，该参考设计可在最轻负载电流下将效率提高 7.2%，从而实现 125.25dB 的 SFDR、99dB 的 SNR 和 16.1 的 ENOB。
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High-efficiency: low-emission: isolated DC/DC converter-based analog input module reference design
This reference design is a simplified architecture for generating an isolated power supply for isolated amplifiers for measuring isolated voltages and currents. A fully integrated DC/DC converter with reinforced isolation operating from a 5-V input with configurable 5-V or 5.4-V output (headroom for low dropout regulator (LDO)) generates the isolated power. Shunts that are interfaced to ±50-mV input range isolation amplifiers configured as channel isolated inputs measure the current. Potential divider output interfaced to ±250-mV or ±12-V input range isolation amplifiers configured as group isolated inputs measure the voltage. The outputs of the isolation amplifiers interface directly to 24-bit delta sigma analog-to-digital converter (ADC) or are scaled to ±10 V using gain amplifiers and interfaced to 16-bit SAR ADC for performance evaluation. On-board digital diagnostics improves reliability and enhances system performance.
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20-bit 1MSPS DAQ Reference Design Optimizing Power Supply Efficiency While Minimizing EMI
This reference design for high performance data acquisition (DAQ) systems optimizes power stage in order to reduce power consumption and minimize the effect of EMI from switching regulator by using LMS3635-Q1 buck converter. This reference designs yields 7.2% efficiency improvement at most light load current compared to LM53635 buck converter: which achieves 125.25dB SFDR: 99dB SNR and 16.1ENOB.
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PMP7877 用于 Xilinx® Zynq-7000 的电源参考设计
This is a multi-output buck converter design that has an input voltage range of 10.8Vin to 13.2Vin and has seven regulated outputs: 1Vout @ 5A, 1.8Vout @ 2.5A, 1.5Vout @ 6A, 3.3Vout @ 5A, 3.3Vout @ 5A, 5Vout @ 2A, and 0.75Vout @ 1A continous/3Apeak. This design has been approved and tested by Xilinx.
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PMP4234 36VDC-75VDC 输入、3.3V/30A 1/8 砖型有源钳位正向
此参考设计可从标准 48V 电信总线输入生成隔离型 3.3V/10A 输出。UCC2897A 用于控制具有自驱同步整流器的有源钳正向拓扑。电气组件装入标准 1/8 引脚砖型的区域。峰值效率超过 92%。
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Reference Design Maximizing Signal Dynamic Range for True 10 Vpp Differential Input to 20 bit ADC
This reference design is designed for high performance data acquisition(DAQ) systems to improve the dynamic range of 20 bit differential input ADCs. Many DAQ systems require the measurement capability at a wide FSR (Full Scale Range) in order to obtain sufficient signal dynamic range. Many earlier reference designs for SAR ADCs have used the THS4551 FDA (fully differential amplifier). However: the THS4551 is limited to a 5.4V maximum supply which is not sufficient for realizing the true 10Vpp differential output (10V FSR) required to maximize the dynamic range of SAR ADCs with a 5V reference. This reference design explores the benefits of a true 10Vpp differential output by implementing TI's new THS4561 FDA which has a maximum supply of 12.6V. You will see that this design was able to achieve superior performance to the previous design (TIDA-01054) while also lowering overall power consumption.
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Smart brake control and diagnostics reference design for servo drives and robotics
This reference design implements safe brake control functionality in servo drives as per IEC EN 61800-5-2 by providing two channel output signals to control an external holding brake. The holding brake will be latched when the power supply is cut off and released when voltage is applied to the coil. This is accomplished by enabling/disabling the smart electronic load switches that supply power to the coil. This reference design also includes diagnostic features for detecting various faults: ensuring safe operation. TIDA-01600 uses the C2000 Launchpad to generate the brake control signals and to perform the diagnostics functionality.
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ADC Voltage Reference Buffer Optimization Reference Design for High Performance DAQ Systems
The TIDA-01055 reference design for high performance DAQ Systems optimizes the ADC reference buffer to improve SNR performance and reduce power consumption with the TI OPA837 high-speed op amp. This device is used in a composite buffer configuration and provides a 22% power improvement over traditional op amps. Voltage reference sources with an integrated buffer often lack the drive strength required to achieve optimal performance in a high-channel count systems. This reference design is capable of driving several ADCs: and achieves a system ENOB of 15.77 bits using an 18-bit: 2-MSPS SAR ADC.
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PMP11180 具有 4 路 POL 输出且轻载效率较高的 120V 交流输入、25W/5V 直流输出参考设计
This 25-W design uses the UCC28740 in a flyback topology to minimize no-load standby power and the UCC24636 synchronous rectifier controller to minimize power MOSFET body-diode conduction times. The design also features point-of-load converters from the main 5V rail that implement an energy-savin
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PMP5515 适用于工业应用的隔离式反激 (24V@2mA)
此参考设计是采用通用线路的多输出隔离型反激式设计。主要稳压输出为 3.3V (350mA)，5V 和 12V 输出通过线性稳压器进行调节，24V 输出采用一个小型电荷泵产生。转换器利用共源共栅反激式拓扑技术和准谐振工作模式，在轻负荷情况下可提供低 EMI 和高效率。
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Two-Wire Interface to a HIPERFACE DSL® Encoder Reference Design
The TIDA-00177 reference design is an EMC compliant industrial interface to a two-wire HIPERFACE DSL® encoder. Applications include industrial servo drives.The design features a 3.3-V supply RS485 transceiver and line termination and coupling for encoder power over RS485 as per HIPERFACE DSL specification. The design has been tested up to 100m cable length with an integrated cable: where the encoder’s two-wire twisted pair was integrated in the same motor cable. The encoder connector output is protected against over-voltage and short circuit to prevent damage to an encoder or during a cable short. The design features an industrial compliant 24-V input with wide range from 18-36V. A 3.3V I/O connector with logic signals for easy interface to a host processor with HIPERFACE DSL Master IP Core is made available.
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Flat-Clamp TVS based Reference Design for Protection Against Transient for Grid Applications
This reference design features multiple approaches for protecting AC or DC analog input: DC analog output: AC or DC binary input: digital output with a high side or low side driver: LCD bias supply: USB interfaces (power and data) and onboard power supplies with 24: 12 or 5V input used in multiple grid applications against overvoltage: overload and transients (1.2/50 us: 42-Ω) using flat-clamp surge protection: ESD devices: eFuse or a load switch. The design monitors temperature: humidity: magnetic fields and power supplies for diagnostics.
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Multi-Rail Power Reference Design for Eliminating EMI Effects in High Performance DAQ Systems
The TIDA-01054 reference design helps eliminate the performance degrading effects of EMI on Data Acquisition (DAQ) systems greater than 16 bits with the help of the LM53635 buck converter. The buck converter enables the designer to place power solutions close to the signal path without the unwanted noise degradation of EMI while saving board space. This design allows for a system SNR performance of 100.13 dB using a 20-bit: 1-MSPS SAR ADC: which almost matches the 100.14 dB SNR performances when using external power sources.
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TIDA-01024 适用于雷达和 5G 无线测试仪的高通道数 JESD204B 菊链时钟参考设计
高速多通道应用需要低噪声、可扩展且可进行精确通道间偏斜调节的时钟解决方案，以实现最佳系统 SNR、SFDR 和 ENOB。此参考设计支持在菊链配置中增加 JESD204B 同步时钟。此设计可提供多通道 JESD204B 时钟，采用 TI LMK04828 时钟抖动清除器和带有集成式 VCO 的 LMX2594 宽带 PLL，能够实现低于 10ps 的时钟间偏斜。此设计经过 TI ADC12DJ3200 EVM 在 3GSPS 环境中检测，具有改善的 SNR 性能，通道间偏斜低于 50ps。本文对所有重要设计理论都进行了阐释说明，可指导用户完成器件选择流程和设计优化。最后，此设计还包含原理图、板布局、硬件测试和测试结果。
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Interface to a 5-V BiSS position encoder reference design
This reference design implements a hardware interface based on the BiSS standard for position or rotary encoders. It supports both BiSS point-to-point and BiSS bus configurations. The building blocks include the power supply for a 5-V BiSS encoder with innovative smart eFuse technology and robust full-duplex RS-485 transceivers including line termination and EMC protection. An auxiliary power supply and logic level interface with adjustable I/O voltage level is provided to connect to subsequent MCUs and MPUs that would run the BiSS (or SSI) master protocol stack. This design is fully tested to meet EMC immunity requirements for ESD: fast-transient burst and surge according to IEC61800-3.
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PMP4751 55V 至 90V 直流输入、5V/10A 有源钳位正向
此参考设计使用 UCC2897A 有源钳控制器在 55V 至 90V 输入范围内生成隔离型 5V/50W 输出。同步整流器可使该转换器实现高达 93% 的效率。
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Reference Design for an Interface to a Position Encoder with EnDat 2.2
This reference design implements a hardware interface based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The building blocks include the power supply for the encoder with innovative smart eFuse technology and robust half-duplex RS-485 transceivers including line termination and EMC protection. An auxiliary power supply and logic level interface with adjustable I/O voltage level are provided to connect to subsequent MCUs and MPUs that would run the EnDat 2.2 master protocol stack. This design is fully tested to meet EMC immunity requirements for ESD: fast transient burst and surge according to IEC61800-3.
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Optimized Analog Front End DAQ System Reference Design for 18 bit SAR Data Converters
The TIDA-01050 reference design aims to improve the integration: power consumption: performance: and clocking issues typically associated with automatic test equipment. This design is applicable to any ATE system but most applicable to systems requiring a large number of input channels.
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ADC Driver Reference Design Improving Full Scale THD Using Negative Supply
The TIDA-01052 reference design aims to highlight system performance increases seen using a negative voltage rail on the analog front end driver amplifiers rather than ground. This concept is relative to all analog front ends: however this design is aimed specifically at automatic test equipment.
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