Part Details for LMK04828 by Texas Instruments

For wideband receiver system developers currently using FPGA or ASIC to connect High Speed data converters to a baseband processor: who need faster time to market with increased performance and significant reduction in cost: power: and size. This reference design includes the first widely available processor integrating a JESD204B interface and Digital Front End Processing (DFE). Connecting ADC32RF80 to DAC38J84 provides an efficient solution for avionics and defense: test and measurements and industrial applications.

This reference design discusses the use and performance of the Ultra-Wideband: Fixed-gain high-speed amplifier: the LMH3401 to drive the high-speed analog-to-digital converter (ADC): the ADS54J60 device. Different options for common-mode voltages: power supplies: and interfaces are discussed and measued: including AC-coupling and DC-coupling: to meet the requirements of a variety of applications.

该参考设计的主要目的是展示基于 TPS92314 的具有 PFC 的超高性能离线 LED 驱动器。该 LED 驱动器旨在将交流输入转换为 LED 调节电流。该参考设计的工作条件和性能如下：●198VAC 至 264VAC、50Hz 输入电压 ●110V 至 130V LED 电压 ●160mA LED 调节电流 ●92% 典型的系统效率 ●高功率因数 > 0.9 ●输出短路和开路保护

A system example to show how to control a stepper motor via Wi-Fi connectivity. The TM4C123x MCU is integrated with the DRV8833 stepper motor driver to drive the stepper motor in full step, half step and microstep (up to 256) modes. The SimpleLink™ Wi-Fi CC3100 network processor is also int

Low cost: high performance clocking solution for GSPS data converters. This reference design discusses the use of a TRF3765: a low noise frequency synthesizer: generating the sampling clock for a 4 GSPS analog-to-digital converter (ADC12J4000). Experiments demonstrate data sheet comparable SNR and SFDR performance.

TIDA-01016 is a clocking solution for high dynamic range high speed ADC. RF input signals are directly captured using the RF sampling approach by high speed ADC. The ADC32RF45 is a dual- channel: 14-bit: 3-GSPS RF sampling ADC. The 3-dB input bandwidth is 3.2 GHz: and it captures signals up to 4 GHz. This design showcases the clocking solution using the LMX2582: to achieve the best SNR performance of ADC32RF45 at higher input frequencies used in microwave backhaul applications.

PMP40071 是一款 POL 模块参考设计，适用于直流输入为 8.3V – 14V 的 DSP 和 FPGA 应用。其超高功率密度有助于电力系统在保持小巧外形的同时处理高功率输送。由于它可通过远程电阻器调整输出电压，因此对各种不同应用具有良好的设计灵活性。此设计还在低温和高温条件下进行了验证。

负电压 TPS7A3001 LDO 与正电压 TPS7A4901 LDO 搭配，可为设计人员提供高精度供电模拟应用程序的完整解决方案。这些 LDO 具有超高的 PSRR 性能，输出噪声可低至 16 µVrms，设计用于为噪声敏感应用程序（如，运算放大器、ADC、DAC 和其它高性能模拟电路）供电。

Employing equalization techniques is an effective way of compensating for channel loss in JESD204B high speed serial interfaces for data converters. This reference design features the ADC16DX370: a dual 16-bit: 370 MSPS analog-to-digital converter (ADC) that utilizes de-emphasis equalization to prepare the 7.4 Gbps serial data for transmission. Configuration allows a user to optimize the de-emphasis setting (DEM) and output voltage swing setting (VOD) of the output driver to inversely match the characteristics of the channel. Experiments demonstrate the reception of a clean data eye over 20” of FR-4 material at the full data rate.

Analog front end for high-speed end equipments like phased-array radars: wireless communication testers: and electronic warfare require synchronized: multipletransceiver signal chains. Each transceiver signal chain includes high-speed: analog-to-digital converters (ADCs): digital-to-analog converters (DACs): and a clock subsystem. The clock subsystem provides low noise sampling clocks with precise delay adjustment to achieve lowest channel-to-channel skew and optimum system performance like signal-to-noise ratio (SNR): spurious free dynamic range (SFDR): IMD3: effective number of bits (ENOB): and so forth. This reference design demonstrates multichannel JESD204B clocks generation and system performance with AFE7444 EVMs. Channel-to-channel skew better than 10 ps achieved with 6 GSPS/3 GSPS DAC/ADC clocks up to 2.6-GHz radio frequencies and system performance like SNR and SFDR are comparable to the AFE7444 data sheet specifications.

The PMP10852 reference design uses the LM5117, CSD18563 for the high side MOSFET and CSD18532 (x2) for the low side MOSFETs.  PMP10852 takes input voltages between 27V to 41V and outputs 180W(12V @15A).  The size is very small, total area is 1,200mm2 (30mm x 40mm) solution size. The des

The LDC1314's unique inductive sensing capability is used to implement a contactless rotational position sensing solution that is accurate to 1 degree. It uses standard PCB technology and easily manufactured components to implement a low cost solution. This reference desig

This reference design consists of an analog front-end (AFE) signal chain for wideband receiver applications using the LMH2832 digitally controlled variable gain amplifier (DVGA) and ADS54J40 analog-to-digital converter (ADC). The design is primarily targeted for upstream DOCSIS 3.1 receiver applications specified for cable modem termination systems (CMTS) and supports up to 196 MHz of upstream signal bandwidth. The circuit solves the filtering and analog signal processing requirements for the DOCSIS 3.1 standard: which makes it easier for system designers to readily incorporate the design on the CMTS-side of the upstream signal path.

This reference design: an 8-channel analog front end (AFE): is demonstrated using two AFE7444 4-channel RF transceivers and a LMK04828-LMX2594 based clocking subsystem which can enable designs to scale to 16 or more channels. Each AFE channel consists of a 14-bit: 9-GSPS DAC and a 3-GSPS ADC that is synchronized to less than 10ps skew with > 75-dB dynamic range at 2.6 GHz.

In order to provide system designers a new cost-effective and easy alternative to assured precision temperature measurement, this reference design discusses the new tiny 2-pin digital output IC temperature sensor with single wire pulse count interface that enhances reliability and greatly simplif

Complete PMBus power system for 3 ASIC/FPGA cores, DDR3 core memory, and auxiliary voltages found on high-performance Ethernet Switches.

This reference design demonstrates how to implement and interface Non Volatile Memory and SDRAM to the performance microcontroller TM4C1294NCPDT in TM4C product family. The implementation is made possible by using the EPI Interface of the Microcontroller to interface a 256Mbit SDRAM at 60MHz and

This reference design details a display power circuit which generates a bipolar voltage rail for source drivers and additional supplies for gate drivers. Charge pumps are used to generate the voltage supply for gate drivers, which makes this design easy to implement. By using only one dc-dc conve

TI 参考设计 TIDA-00666 支持蓝牙低功耗 (BLE) 通信，并通过电流为 4-20mA 的双线回路供电。对于工业过程控制仪表，4mA 至 20mA 模拟电流回路通常用于传输模拟信号。20mA 和 4mA 分别表示信号范围的上限和下限。TIDA-00666 参考设计测量湿度和温度并通过蓝牙低功耗技术播报测量的值。TIDA-00666 设计采用回路供电方式，且回路中的电流值随湿度值而变化（0% 为 4mA，100% 为 20mA）。

The TSW40RF82EVM reference design provides a platform to interface the DAC38RF82 with a high-performance modulator - the TRF370417EVM. The TRF370417EVM can modulate wideband signals at up to 6 GHz as would be typical for a microwave backhaul application. The TRF370417 device may be substituted for a suitable higher-frequency device. Minimal modification is required to interface the digital-to-analog converter (DAC) with the modulator. This design provides the method to interface the TSW40RF82EVM with the TRF370417EVM.

The PMP10543 reference design is a low profile quad output isolated Fly-Buck power supply for industrial applications.  The power supply has a synchronous buck regulator, LM5017, and a low profile (6mm) transformer. It generates four isolated outputs of ±5V, ±12V, 75mA each.&nb

PMP7758 是具有 6-20V DC 输入和 3.3V、1A 输出的非同步降压 DC-DC 控制器其为低成本、高效率开关稳压器。其采用包含 N 通道降压开关、启动稳压器、电流限制检测和内部波纹控制的 LM25011。恒准时调整原则无需环路补偿，从而实现快速负载瞬态响应，简化电路实现。

For modern radar system developers currently using an FPGA or ASIC to connect to high speed data converters: who need faster time to market with increased performance and significant reduction in cost: power: and size: this reference design includes the first widely available processor integrating a JESD204B interface and Digital Front End (DFE) processing. Connecting to the ADC14X250 and DAC38J84 provides an efficient solution for avionics and defense applications such radar: electronic warfare: compute platforms and transponders.

This reference design demonstrates an efficient: low noise 5-rail power-supply design for very high-speed DAQ systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency synchronized and phase-shifted in order to minimize input current ripple and control frequency content. Furthermore: any potential radiated electromagnetic interference (EMI) is minimized by using high performance HotRodTM packaging technology.

This reference design discusses the use and performance of the Digital Variable-Gain high-speed amplifier: the LMH6401: to drive the high-speed analog-to-digital converter (ADC): the ADS54J60 device. Different options for common-mode voltages: power supplies: and interfaces are discussed and measued: including AC-coupling and DC-coupling: to meet the requirements of a variety of applications.

This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is achieved by time-terleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs: which this reference design achieves using the Noiseless Aperture Delay Adjustment (tAD Adjust) feature of the ADC12DJ3200. This feature is also used to minimize mismatches typical of interleaved ADCs: maximizing SNR: ENOB: and SFDR performance. A low phase noise clocking tree with JESD204B support is also featured on this reference design: and it is implemented using the LMX2594 wideband PLL and the LMK04828 synthesizer and jitter cleaner.

PMP8000 is a single-phase synchronous buck converter rated for 5V output at 30A from an input voltage of 12V. This design uses the LM27403 synchronous buck controller and CSD87350Q5D power block MOSFETs provide maximum efficiency when combined with a 250nH ferrite output inductor. The design solu

This discrete power supply reference design demonstrates a complete power solution for the Freescale™ MPC5748G Microcontroller. This simple discrete solution uses just five DC/DC converters: it offers a more flexible: scalable and cost-effective solution than when using a PMIC. This TI Design supports numerous automotive applications such as gateway and central body control modules.

This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation: which affects overall system SNR: SFDR: channel to channel skew and deterministic latency. This reference design demonstrates multi-channel AFE and clock solution using high speed data converters with JESD204B: high speed amplifiers: high performance clocks and low noise power solutions to achieve optimum system performance

A direct RF sampling receiver approach to a radar system operating in S-band is demonstrated using the ADC32RF45: 3-Gsps: 14-bit analog to digital converter (ADC). RF sampling reduces the complexity of a system by removing down conversion and using a high sampling rate enables wider signal bandwidths. The approach is demonstrated by building a receiver based on the ASR-11 air traffic control radar specifications.

This reference design demonstrates the performance of a reinforced, isolated, full-duplex M-LVDS transceiver node using the ISO7842 and SN65MLVD203. A single reinforced digital isolator replaces two basic digital isolators, reducing cost and PCB area.

This reference design provides the solution for synchronization design challenges associated with emerging 5G adapted applications like massive multiple input multiple output (mMIMO): phase array RADAR and communication payload. The typical RF front end contains antenna: low noise amplifier (LNA): mixer : local oscillator (LO) in analog domain and analog to digital converter: numerical controlled oscillator (NCO) and digital down converter (DDC) in digital domain. To achieve overall system synchronization these digital blocks need to be synchronize with system clock. This reference design uses ADC12DJ3200 data converter: achieve less than 5-ps channel-to-channel skew across multiple receiver with deterministic latency by synchronizing on chip NCO with SYNC~ and uses noiseless aperture delay adjustment (tAD Adjust) feature to further reduce skew. This design also provides a very low phase noise clocking solution based the LMX2594 wide band PLL and the LMK04828 synthesizer and jitter cleaner.

The TIDA-01015 is a clocking solution reference design for high speed direct RF sampling GSPS ADCs. This design showcases the significance of the sampling clock to achieve high SNR for 2nd Nyquist zone input signal frequencies. ADC12J4000 is a 12-bit: 4-GSPS RF sampling ADC with 3-dB input bandwidth of 3.2 GHz capable of capturing signals up to 4 GHz. This design highlights a clocking solution for the ADC12J4000 using TRF3765: to achieve high SNR performance at high input frequencies used in applications such as digital storage oscilloscopes (DSO) and wireless testers.

This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate: however: matching individual ADCs offset: gain and sampling time mismatch is critical to achieve performance. The complexity of interleaving increases with higher sampling clock. The phase matching between the ADCs is one of the critical specifications to achieve better SFDR and ENOB. This reference design uses the noiseless aperture delay adjustment feature on ADC12DJ5200RF with a 19 fs precise phase control steps that eases 20.8 GSPS interleaving implementation. The reference design uses on-board low noise JESD204B clock generator based on LMK04828 and LMX2594 that meets 12 bit system performance requirement.

This reference design provides an efficient power supply scheme to power-up the RF-sampling DAC38RF8x digital-to-analog data converter (DAC) without sacrificing performance and also reduces board area and BOM. The reference design uses both DC/DC switchers and an LDO to power-up the DAC38RF8x while achieving high analog performance (spurious and phase noise) and minimizing power efficiency trade-offs. The design method outlined here can be extended to the power supply design of other RF-sampling data converters.

PMP9484 is a 100W highly efficient and compact automotive amplifier reference design which can be used in 50W +50W stereo or 100W woofer applications.  The design is broadly divided into three main stages:1.) Highly efficient single-phase synchronous boost converter using the LM5122 co

PMP7040.1(20V@0.25A) 参考设计是面向 3 相智能仪表（147-400VAC，20V@0.25A）的隔离型 DCM 反激式 - 使用 UCC28610 的多输出反激式，主要用于计量应用。可以从使用 147 到 400 伏特交流电的输入生成隔离式 20 伏特输出（0.25 安培）。该设计有多个输出。

TIDA-01353 参考设计是一种基于 MOSFET 的分立式三相 ECM 控制模块，适用于在 HVAC 风机应用中使用无传感器梯形控制方法驱动额定功率高达 375W 的无刷 (BLDC) 电机。逐周期过流保护功能可保护功率级不受过流影响，而且板可以在高达 85°C 的环境温度下工作。此设计还针对用户可用的 5 个预设风机转速端子包含光电隔离，并且是对永久分相式电容器 (PSC) 电机的一种直接替代参考设计。

High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR: SFDR: and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 wideband PLL with integrated VCOs to generate a 10 MHz to 15 GHz clock and SYSREF for JESD204B interfaces. The 10 KHz offset phase noise is < -104 dBc/Hz for a 15 GHz clock frequency.  By using TI’s ADC12DJ3200 high speed converter EVMs: a board-to-board clock skew of <10ps is achieved and a SNR of 49.6 dB with a 5.25 GHz input signal. All key design theories are described: guiding users through the part selection process and design optimization.  Finally: schematic: board layout: hardware testing: and results are also presented.

The RF sampling receiver captures signals directly in the radio frequency (RF) band. In a multi-band application the desired signals are not very wide band but they are spaced far apart within the spectrum. The reference design captures signals in different RF bands and digitally down-converts them to baseband.The reference design showcases the ADC32RF80 dual channel: 14-bit: 3-GSPS RF sampling telecom receiver. The device includes two digital down converters (DDC) per channel. The DDC offers decimation values from 8 to 32 and includes a 16-bit numerically controlled. With the high sampling rate of the ADC32RF80 the reference design captures a large swatch of RF spectrum which contains signals in multiple bands and potentially undesired interferers. The DDC independently mixes the desired bands to digital baseband. Decimation reduces the output data rate to a lower level and provides digital filtering around the desired band to eliminate interference and to improve signal-to-noise ratio performance. This feature is critical for high end telecommunication receivers that require high dynamic range.

TIDA-01235 参考设计的主要目的是提供一种高密度、低成本、高精度的热电偶模拟前端。设计中包含的保护策略可保护模拟前端不受耦合瞬态影响。此设计满足汽车尾气温度传感器的要求。