We use Cookies to give you best experience on our website. By using our website and services, you expressly agree to the placement of our performance, functionality and advertising cookies. Please see our Privacy Policy for more information.

Register or Sign In
Microcontrollers and Processors / Multifunction Peripherals / FDC37C932FR
Datasheets
FDC37C932FR by: SMSC

Multifunction Peripheral, CMOS, PQFP160, QFP-160

Part Details for FDC37C932FR by SMSC

Results Overview of FDC37C932FR by SMSC

Tip: Data for a part may vary between manufacturers. You can filter for manufacturers on the top of the page next to the part image and part number.

Applications Space Technology Aerospace and Defense Automotive

FDC37C932FR Information

FDC37C932FR by SMSC is a Multifunction Peripheral.
Multifunction Peripherals are under the broader part category of Microcontrollers and Processors.

Microcontrollers (MCUs) are small, low-power integrated circuits used to control embedded systems. Microcontrollers are primarily used to automate and control devices. Read more about Microcontrollers and Processors on our Microcontrollers and Processors part category page.

Price & Stock for FDC37C932FR

Part # Distributor Description Stock Price Buy
Quest Components Controller Miscellaneous - Datasheet Reference 352
  • 1 $11.2600
  • 143 $6.7560
  • 297 $6.4745
$6.4745 / $11.2600 Buy Now

Part Details for FDC37C932FR

FDC37C932FR CAD Models

There are no models available for this part yet.

Sign in to request this CAD model.

Register or Sign In

FDC37C932FR Part Data Attributes

Parametric Data
FDC37C932FR SMSC
Buy Now Datasheet
Compare Parts:
FDC37C932FR SMSC Multifunction Peripheral, CMOS, PQFP160, QFP-160
Select a part to compare:
Rohs Code No
Part Life Cycle Code Obsolete
Ihs Manufacturer STANDARD MICROSYSTEMS CORP
Part Package Code QFP
Package Description QFP-160
Pin Count 160
Reach Compliance Code unknown
HTS Code 8542.39.00.01
Address Bus Width 12
Boundary Scan NO
Bus Compatibility PC-XT; PC-AT; ISA; PS/2
Clock Frequency-Max 14.318 MHz
External Data Bus Width 8
JESD-30 Code S-PQFP-G160
Length 28 mm
Number of I/O Lines 14
Number of Terminals 160
Operating Temperature-Max 70 °C
Operating Temperature-Min
Package Body Material PLASTIC/EPOXY
Package Code QFP
Package Shape SQUARE
Package Style FLATPACK
Peak Reflow Temperature (Cel) 235
Qualification Status Not Qualified
RAM (words) 256
Seated Height-Max 4.07 mm
Supply Voltage-Max 5.5 V
Supply Voltage-Min 4.5 V
Supply Voltage-Nom 5 V
Surface Mount YES
Technology CMOS
Temperature Grade COMMERCIAL
Terminal Form GULL WING
Terminal Pitch 0.65 mm
Terminal Position QUAD
Width 28 mm

FDC37C932FR Related Parts

FDC37C932FR Frequently Asked Questions (FAQ)

  • The recommended operating temperature range for the FDC37C932FR is -40°C to 85°C, as specified in the datasheet. However, it's essential to note that the device can operate at temperatures beyond this range, but with reduced performance and reliability.

  • The FDC37C932FR can operate in either I2C or SMBus mode. To configure the device for I2C operation, connect the SCL pin to a pull-up resistor and the SDA pin to a pull-up resistor or an open-drain output. For SMBus operation, connect the SCL pin to a pull-up resistor and the SDA pin to a pull-up resistor or an open-drain output, and ensure that the SMBus clock stretching is enabled.

  • The FDC37C932FR supports clock frequencies up to 400 kHz in I2C mode and up to 100 kHz in SMBus mode. However, it's recommended to operate the device at a clock frequency of 100 kHz or lower to ensure reliable operation and minimize power consumption.

  • The FDC37C932FR has a built-in POR and BOR feature that resets the device during power-on or brown-out conditions. To handle these features, ensure that the power supply voltage is stable and within the recommended operating range. Also, implement a power-on reset circuit or a brown-out detection circuit to detect and respond to these events.

  • Yes, the FDC37C932FR can operate in a multi-master I2C or SMBus configuration. However, it's essential to ensure that each master device has a unique address and that the bus is properly arbitrated to prevent data corruption or bus contention.