Part Details for L63500A0GC-30 by Avago Technologies
Overview of L63500A0GC-30 by Avago Technologies
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Part Details for L63500A0GC-30
L63500A0GC-30 CAD Models
L63500A0GC-30 Part Data Attributes
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L63500A0GC-30
Avago Technologies
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L63500A0GC-30
Avago Technologies
IC,MIL-STD-1553/ARINC BUS CONTROLLER/RTU,CMOS,PGA,180PIN
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Rohs Code | No | |
Part Life Cycle Code | Active | |
Ihs Manufacturer | AVAGO TECHNOLOGIES INC | |
Package Description | PGA, PGA180M,15X15 | |
Reach Compliance Code | compliant | |
HTS Code | 8542.31.00.01 | |
Address Bus Width | ||
Boundary Scan | NO | |
Communication Protocol | ASYNC, BIT | |
External Data Bus Width | ||
JESD-30 Code | S-XPGA-P180 | |
JESD-609 Code | e0 | |
Number of Serial I/Os | 1 | |
Number of Terminals | 180 | |
Operating Temperature-Max | 70 °C | |
Operating Temperature-Min | ||
Package Body Material | CERAMIC | |
Package Code | PGA | |
Package Equivalence Code | PGA180M,15X15 | |
Package Shape | SQUARE | |
Package Style | GRID ARRAY | |
Qualification Status | Not Qualified | |
Supply Voltage-Max | 5.25 V | |
Supply Voltage-Min | 4.75 V | |
Supply Voltage-Nom | 5 V | |
Surface Mount | NO | |
Technology | CMOS | |
Temperature Grade | COMMERCIAL | |
Terminal Finish | Tin/Lead (Sn/Pb) | |
Terminal Form | PIN/PEG | |
Terminal Pitch | 2.54 mm | |
Terminal Position | PERPENDICULAR | |
uPs/uCs/Peripheral ICs Type | SERIAL IO/COMMUNICATION CONTROLLER, SERIAL |