Datasheets
ICE40LP384-CM36 by: Lattice Semiconductor Corporation

Field Programmable Gate Array, CMOS, PBGA36, UCBGA-36

Part Details for ICE40LP384-CM36 by Lattice Semiconductor Corporation

Results Overview of ICE40LP384-CM36 by Lattice Semiconductor Corporation

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Applications Computing and Data Storage

ICE40LP384-CM36 Information

ICE40LP384-CM36 by Lattice Semiconductor Corporation is a Field Programmable Gate Array.
Field Programmable Gate Arrays are under the broader part category of Programmable Logic Devices.

Programmable Logic Devices (PLDs) are reconfigurable digital components that can be customized for different applications, offering flexibility and improved performance over fixed logic devices. Read more about Programmable Logic Devices on our Programmable Logic part category page.

Price & Stock for ICE40LP384-CM36

Part # Distributor Description Stock Price Buy
DISTI # 54AJ9732
Newark Ice40 Lp Ultra Low-Power, 384 Luts, 1.2V Rohs Compliant: Yes |Lattice Semiconductor ICE40LP384-CM36 RoHS: Compliant Min Qty: 4900 Package Multiple: 1 Date Code: 0 Container: Bulk 0
  • 500 $2.4600
$2.4600 Buy Now
DISTI # 220-2649-ND
DigiKey IC FPGA 25 I/O 36UCBGA Min Qty: 4900 Lead time: 16 Weeks Container: Tray Temporarily Out of Stock
  • 4,900 $2.4050
$2.4050 Buy Now
DISTI # 842-ICE40LP384CM36
Mouser Electronics FPGA - Field Programmable Gate Array iCE40LP Ultra LowPwr 384 LUTs 1.2V RoHS: Compliant 0
  • 4,900 $2.4100
$2.4100 Order Now
DISTI # V36:1790_06798011
Arrow Electronics FPGA iCE40 LP Family 384 Cells 40nm Technology 1.2V 36-Pin UCBGA Tray RoHS: Compliant Min Qty: 1 Package Multiple: 1 Lead time: 16 Weeks Date Code: 1806 Americas - 4900
  • 1 $2.3980
  • 4,900 $2.3840
$2.3840 / $2.3980 Buy Now
DISTI # 86895803
Verical FPGA iCE40 LP Family 384 Cells 40nm Technology 1.2V 36-Pin UCBGA Tray RoHS: Compliant Min Qty: 3 Package Multiple: 1 Date Code: 1806 Americas - 4900
  • 3 $2.3980
  • 4,900 $2.3840
$2.3840 / $2.3980 Buy Now
Flip Electronics Stock 13570
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Part Details for ICE40LP384-CM36

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ICE40LP384-CM36 Part Data Attributes

ICE40LP384-CM36 Lattice Semiconductor Corporation
Buy Now Datasheet
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ICE40LP384-CM36 Lattice Semiconductor Corporation Field Programmable Gate Array, CMOS, PBGA36, UCBGA-36
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Rohs Code Yes
Part Life Cycle Code Active
Ihs Manufacturer LATTICE SEMICONDUCTOR CORP
Package Description VFBGA,
Reach Compliance Code compliant
ECCN Code EAR99
HTS Code 8542.31.00.01
Samacsys Manufacturer Lattice Semiconductor
Combinatorial Delay of a CLB-Max 9.36 ns
JESD-30 Code S-PBGA-B36
JESD-609 Code e1
Length 2.5 mm
Moisture Sensitivity Level 3
Number of CLBs 48
Number of Inputs 25
Number of Logic Cells 384
Number of Outputs 25
Number of Terminals 36
Operating Temperature-Max 100 °C
Operating Temperature-Min -40 °C
Organization 48 CLBS
Package Body Material PLASTIC/EPOXY
Package Code VFBGA
Package Equivalence Code BGA36,6X6,16
Package Shape SQUARE
Package Style GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Cel) NOT SPECIFIED
Programmable Logic Type FIELD PROGRAMMABLE GATE ARRAY
Seated Height-Max 1 mm
Supply Voltage-Max 1.26 V
Supply Voltage-Min 1.14 V
Supply Voltage-Nom 1.2 V
Surface Mount YES
Technology CMOS
Temperature Grade INDUSTRIAL
Terminal Finish Tin/Silver/Copper (Sn/Ag/Cu)
Terminal Form BALL
Terminal Pitch 0.4 mm
Terminal Position BOTTOM
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Width 2.5 mm

ICE40LP384-CM36 Related Parts

ICE40LP384-CM36 Frequently Asked Questions (FAQ)

  • Lattice provides a PCB design guide and layout recommendations in their documentation, including guidelines for signal integrity, power distribution, and thermal management. It's essential to follow these guidelines to ensure reliable operation and minimize signal degradation.

  • To optimize power consumption, use the Lattice Power Calculator tool to estimate power consumption based on your design requirements. Implement power-saving techniques such as clock gating, voltage scaling, and dynamic voltage and frequency scaling. Additionally, use the FPGA's built-in power management features, such as the Power Manager IP core.

  • The ICE40LP384-CM36 has a maximum clock frequency of 200 MHz, and signal integrity can be affected by factors such as signal skew, jitter, and crosstalk. To mitigate these effects, use the FPGA's built-in clock domain crossing (CDC) and signal conditioning features, and follow Lattice's guidelines for clock tree synthesis and signal routing.

  • Use the Lattice Diamond software to generate a reliable configuration bitstream, and follow the recommended programming and configuration procedures outlined in the datasheet and user manual. Ensure that the FPGA is properly powered and clocked during configuration, and use the built-in configuration error detection and correction features.

  • The ICE40LP384-CM36 has a maximum junction temperature of 100°C. Ensure that the FPGA is properly cooled using a heat sink or other thermal management solution, and follow Lattice's guidelines for thermal design and analysis. Monitor the FPGA's temperature using the built-in thermal sensor and adjust the cooling solution as needed.