Part Details for 74LVC02APW-Q100J by NXP Semiconductors
Overview of 74LVC02APW-Q100J by NXP Semiconductors
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Part Details for 74LVC02APW-Q100J
74LVC02APW-Q100J CAD Models
74LVC02APW-Q100J Part Data Attributes
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74LVC02APW-Q100J
NXP Semiconductors
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74LVC02APW-Q100J
NXP Semiconductors
74LVC02A-Q100 - Quad 2-input NOR gate TSSOP 14-Pin
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| Rohs Code | Yes | |
| Part Life Cycle Code | Transferred | |
| Ihs Manufacturer | NXP SEMICONDUCTORS | |
| Part Package Code | TSSOP | |
| Package Description | 4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14 | |
| Pin Count | 14 | |
| Manufacturer Package Code | SOT402-1 | |
| Reach Compliance Code | compliant | |
| Family | LVC/LCX/Z | |
| JESD-30 Code | R-PDSO-G14 | |
| Length | 5 mm | |
| Load Capacitance (CL) | 50 pF | |
| Logic IC Type | NOR GATE | |
| Max I(ol) | 0.024 A | |
| Number of Functions | 4 | |
| Number of Inputs | 2 | |
| Number of Terminals | 14 | |
| Operating Temperature-Max | 125 °C | |
| Operating Temperature-Min | -40 °C | |
| Package Body Material | PLASTIC/EPOXY | |
| Package Code | TSSOP | |
| Package Equivalence Code | TSSOP14,.25 | |
| Package Shape | RECTANGULAR | |
| Package Style | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH | |
| Packing Method | TR | |
| Prop. Delay@Nom-Sup | 5.5 ns | |
| Propagation Delay (tpd) | 10.1 ns | |
| Qualification Status | Not Qualified | |
| Schmitt Trigger | NO | |
| Screening Level | AEC-Q100 | |
| Seated Height-Max | 1.1 mm | |
| Supply Voltage-Max (Vsup) | 3.6 V | |
| Supply Voltage-Min (Vsup) | 1.65 V | |
| Supply Voltage-Nom (Vsup) | 3.3 V | |
| Surface Mount | YES | |
| Technology | CMOS | |
| Temperature Grade | AUTOMOTIVE | |
| Terminal Form | GULL WING | |
| Terminal Pitch | 0.65 mm | |
| Terminal Position | DUAL | |
| Width | 4.4 mm |