Part Details for 74AUP2G125GD,125 by NXP Semiconductors
Overview of 74AUP2G125GD,125 by NXP Semiconductors
- Distributor Offerings: (2 listings)
- Number of FFF Equivalents: (0 crosses)
- CAD Models: (Request Part)
- Number of Functional Equivalents: (0 crosses)
- Part Data Attributes: (Available)
- Reference Designs: (Not Available)
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Price & Stock for 74AUP2G125GD,125
Part # | Distributor | Description | Stock | Price | Buy | |
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DISTI #
2156-74AUP2G125GD125-ND
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DigiKey | IC BUFFER/LINEDVR DUAL XSON8U Min Qty: 2049 Lead time: 52 Weeks Container: Bulk MARKETPLACE PRODUCT |
75000 In Stock |
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$0.1500 | Buy Now |
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Rochester Electronics | 74AUP2G125GD - Bus Driver, AUP/ULP/V Series, 2-Func, 1-Bit, True Output, CMOS, PDSO8 ' RoHS: Compliant Status: Obsolete Min Qty: 1 | 5209 |
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$0.1257 / $0.1479 | Buy Now |
Part Details for 74AUP2G125GD,125
74AUP2G125GD,125 CAD Models
74AUP2G125GD,125 Part Data Attributes
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74AUP2G125GD,125
NXP Semiconductors
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Datasheet
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74AUP2G125GD,125
NXP Semiconductors
74AUP2G125 - Low-power dual buffer/line driver; 3-state SON 8-Pin
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Rohs Code | Yes | |
Part Life Cycle Code | Transferred | |
Ihs Manufacturer | NXP SEMICONDUCTORS | |
Part Package Code | SON | |
Package Description | 3 X 2 MM, 0.50 MM HEIGHT, PLASTIC, SOT996-2, SON-8 | |
Pin Count | 8 | |
Manufacturer Package Code | SOT996-2 | |
Reach Compliance Code | compliant | |
Factory Lead Time | 4 Weeks | |
Control Type | ENABLE LOW | |
Family | AUP/ULP/V | |
JESD-30 Code | R-PDSO-N8 | |
JESD-609 Code | e4 | |
Length | 3 mm | |
Load Capacitance (CL) | 30 pF | |
Logic IC Type | BUS DRIVER | |
Max I(ol) | 0.0017 A | |
Moisture Sensitivity Level | 1 | |
Number of Bits | 1 | |
Number of Functions | 2 | |
Number of Ports | 2 | |
Number of Terminals | 8 | |
Operating Temperature-Max | 125 °C | |
Operating Temperature-Min | -40 °C | |
Output Characteristics | 3-STATE | |
Output Polarity | TRUE | |
Package Body Material | PLASTIC/EPOXY | |
Package Code | VSON | |
Package Equivalence Code | SOLCC8,.11,20 | |
Package Shape | RECTANGULAR | |
Package Style | SMALL OUTLINE, VERY THIN PROFILE | |
Packing Method | TR | |
Peak Reflow Temperature (Cel) | 260 | |
Prop. Delay@Nom-Sup | 24 ns | |
Propagation Delay (tpd) | 24 ns | |
Qualification Status | Not Qualified | |
Seated Height-Max | 0.5 mm | |
Supply Voltage-Max (Vsup) | 3.6 V | |
Supply Voltage-Min (Vsup) | 0.8 V | |
Supply Voltage-Nom (Vsup) | 1.1 V | |
Surface Mount | YES | |
Technology | CMOS | |
Temperature Grade | AUTOMOTIVE | |
Terminal Finish | NICKEL PALLADIUM GOLD | |
Terminal Form | NO LEAD | |
Terminal Pitch | 0.5 mm | |
Terminal Position | DUAL | |
Time@Peak Reflow Temperature-Max (s) | 30 | |
Width | 2 mm |