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74AUP2G97 - Low-power dual PCB configurable multiple function gate@en-us TSSOP 10-Pin
Tip: Data for a part may vary between manufacturers. You can filter for manufacturers on the top of the page next to the part image and part number.
Part # | Distributor | Description | Stock | Price | Buy | |
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DISTI #
30AK2262
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Newark | Ic, Quad Buffer Rohs Compliant: Yes |Nexperia 74AUP2G97DPJ RoHS: Compliant Min Qty: 2500 Package Multiple: 1 Date Code: 0 Container: Reel | 0 |
|
$0.3970 | Buy Now |
DISTI #
1727-74AUP2G97DPJCT-ND
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DigiKey | IC GATE DUAL PCB MULTI 10TSSOP Min Qty: 1 Lead time: 8 Weeks Container: Digi-Reel®, Cut Tape (CT), Tape & Reel (TR) |
2412 In Stock |
|
$0.3067 / $0.8700 | Buy Now |
DISTI #
771-74AUP2G97DPJ
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Mouser Electronics | Logic Gates 74AUP2G97DP/SOT552/TSSOP10 RoHS: Compliant | 0 |
|
$0.2820 / $0.3070 | Order Now |
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Future Electronics | 74AUP Series 3.6V 4mA 0.25W Dual PCB Configurable Multiple Function Gate-TSSOP10 RoHS: Compliant pbFree: Yes Min Qty: 5000 Package Multiple: 2500 Lead time: 8 Weeks Container: Reel | 0Reel |
|
$0.2700 / $0.2800 | Buy Now |
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Rochester Electronics | 74AUP2G97DP - Majority Logic Gate, AUP/ULP/V Series, 2-Func, 2-Input, CMOS, PDSO10 RoHS: Compliant Status: Active Min Qty: 1 | 3922 |
|
$0.2521 / $0.2966 | Buy Now |
DISTI #
74AUP2G97DPJ
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TTI | Logic Gates 74AUP2G97DP/SOT552/TSSOP10 RoHS: Compliant pbFree: Pb-Free Min Qty: 2500 Package Multiple: 2500 Container: Reel | Americas - 0 |
|
$0.2830 / $0.3180 | Buy Now |
DISTI #
74AUP2G97DPJ
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Avnet Silica | (Alt: 74AUP2G97DPJ) RoHS: Compliant Min Qty: 2500 Package Multiple: 2500 Lead time: 10 Weeks, 0 Days | Silica - 0 |
|
Buy Now |
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74AUP2G97DPJ
Nexperia
Buy Now
Datasheet
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74AUP2G97DPJ
Nexperia
74AUP2G97 - Low-power dual PCB configurable multiple function gate@en-us TSSOP 10-Pin
|
Rohs Code | Yes | |
Part Life Cycle Code | Active | |
Ihs Manufacturer | NEXPERIA | |
Part Package Code | TSSOP | |
Package Description | TSSOP-10 | |
Pin Count | 10 | |
Manufacturer Package Code | SOT552-1 | |
Reach Compliance Code | compliant | |
Samacsys Manufacturer | Nexperia | |
Family | AUP/ULP/V | |
JESD-30 Code | S-PDSO-G10 | |
JESD-609 Code | e4 | |
Length | 3 mm | |
Logic IC Type | MAJORITY LOGIC GATE | |
Moisture Sensitivity Level | 1 | |
Number of Functions | 2 | |
Number of Inputs | 2 | |
Number of Terminals | 10 | |
Operating Temperature-Max | 125 °C | |
Operating Temperature-Min | -40 °C | |
Package Body Material | PLASTIC/EPOXY | |
Package Code | TSSOP | |
Package Shape | SQUARE | |
Package Style | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH | |
Packing Method | TR, 13 INCH | |
Peak Reflow Temperature (Cel) | 260 | |
Propagation Delay (tpd) | 22.2 ns | |
Seated Height-Max | 1.1 mm | |
Supply Voltage-Max (Vsup) | 3.6 V | |
Supply Voltage-Min (Vsup) | 0.8 V | |
Supply Voltage-Nom (Vsup) | 1.1 V | |
Surface Mount | YES | |
Technology | CMOS | |
Temperature Grade | AUTOMOTIVE | |
Terminal Finish | NICKEL PALLADIUM GOLD | |
Terminal Form | GULL WING | |
Terminal Pitch | 0.5 mm | |
Terminal Position | DUAL | |
Time@Peak Reflow Temperature-Max (s) | 30 | |
Width | 3 mm |