TSX68020VR1B/C25 vs TSX68020MR25 feature comparison

TSX68020VR1B/C25 Teledyne e2v

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TSX68020MR25 Teledyne e2v

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Part Life Cycle Code Obsolete Obsolete
Ihs Manufacturer E2V TECHNOLOGIES PLC E2V TECHNOLOGIES PLC
Part Package Code PGA PGA
Package Description PGA, PGA,
Pin Count 114 114
Reach Compliance Code unknown unknown
HTS Code 8542.31.00.01 8542.31.00.01
Address Bus Width 32 32
Bit Size 32 32
Boundary Scan NO NO
Clock Frequency-Max 25 MHz 25 MHz
External Data Bus Width 32 32
Format FIXED POINT FIXED POINT
Integrated Cache YES YES
JESD-30 Code S-CPGA-P114 S-CPGA-P114
Length 34.54 mm 34.54 mm
Low Power Mode YES YES
Number of Terminals 114 114
Operating Temperature-Max 85 °C 125 °C
Operating Temperature-Min -40 °C -55 °C
Package Body Material CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
Package Code PGA PGA
Package Shape SQUARE SQUARE
Package Style GRID ARRAY GRID ARRAY
Qualification Status Not Qualified Not Qualified
Screening Level MIL-STD-883 Class B
Seated Height-Max 4.82 mm 4.82 mm
Speed 25 MHz 25 MHz
Supply Voltage-Max 5.5 V 5.5 V
Supply Voltage-Min 4.5 V 4.5 V
Supply Voltage-Nom 5 V 5 V
Surface Mount NO NO
Technology HCMOS HCMOS
Temperature Grade INDUSTRIAL MILITARY
Terminal Form PIN/PEG PIN/PEG
Terminal Pitch 2.54 mm 2.54 mm
Terminal Position PERPENDICULAR PERPENDICULAR
Width 34.54 mm 34.54 mm
uPs/uCs/Peripheral ICs Type MICROPROCESSOR MICROPROCESSOR
Base Number Matches 1 1
ECCN Code 3A001.A.2.C
JESD-609 Code e4
Terminal Finish GOLD

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