TDPLD910-15
vs
5962-8854801QA
feature comparison
| Rohs Code |
No
|
|
| Part Life Cycle Code |
Obsolete
|
Obsolete
|
| Ihs Manufacturer |
INTEL CORP
|
ALTERA CORP
|
| Part Package Code |
DIP
|
DIP
|
| Package Description |
DIP, DIP40,.6
|
DIP,
|
| Pin Count |
40
|
40
|
| Reach Compliance Code |
compliant
|
unknown
|
| HTS Code |
8542.39.00.01
|
8542.39.00.01
|
| Additional Feature |
PAL WITH MACROCELLS; 24 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS
|
|
| Architecture |
PAL-TYPE
|
|
| Clock Frequency-Max |
45.4 MHz
|
14.3 MHz
|
| JESD-30 Code |
R-GDIP-T40
|
R-XDIP-T40
|
| JESD-609 Code |
e0
|
|
| Length |
52.325 mm
|
|
| Number of Dedicated Inputs |
12
|
12
|
| Number of I/O Lines |
24
|
24
|
| Number of Inputs |
36
|
|
| Number of Outputs |
24
|
|
| Number of Product Terms |
240
|
|
| Number of Terminals |
40
|
40
|
| Operating Temperature-Max |
85 °C
|
125 °C
|
| Operating Temperature-Min |
-40 °C
|
-55 °C
|
| Organization |
12 DEDICATED INPUTS, 24 I/O
|
12 DEDICATED INPUTS, 24 I/O
|
| Output Function |
MACROCELL
|
MACROCELL
|
| Package Body Material |
CERAMIC, GLASS-SEALED
|
UNSPECIFIED
|
| Package Code |
DIP
|
DIP
|
| Package Equivalence Code |
DIP40,.6
|
|
| Package Shape |
RECTANGULAR
|
RECTANGULAR
|
| Package Style |
IN-LINE
|
IN-LINE
|
| Programmable Logic Type |
UV PLD
|
UV PLD
|
| Propagation Delay |
18 ns
|
60 ns
|
| Qualification Status |
Not Qualified
|
Not Qualified
|
| Seated Height-Max |
5.72 mm
|
|
| Supply Voltage-Max |
5.25 V
|
5.5 V
|
| Supply Voltage-Min |
4.75 V
|
4.5 V
|
| Supply Voltage-Nom |
5 V
|
5 V
|
| Surface Mount |
NO
|
NO
|
| Technology |
CMOS
|
CMOS
|
| Temperature Grade |
INDUSTRIAL
|
MILITARY
|
| Terminal Finish |
TIN LEAD
|
|
| Terminal Form |
THROUGH-HOLE
|
THROUGH-HOLE
|
| Terminal Pitch |
2.54 mm
|
|
| Terminal Position |
DUAL
|
DUAL
|
| Width |
15.24 mm
|
|
| Base Number Matches |
1
|
2
|
| ECCN Code |
|
3A001.A.2.C
|
| Screening Level |
|
MIL-STD-883
|
|
|
|
Compare TDPLD910-15 with alternatives
Compare 5962-8854801QA with alternatives