PUMD2 vs PUMD2,115 feature comparison

PUMD2 Nexperia

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PUMD2,115 NXP Semiconductors

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Rohs Code Yes Yes
Part Life Cycle Code Active Transferred
Ihs Manufacturer NEXPERIA NXP SEMICONDUCTORS
Reach Compliance Code compliant compliant
ECCN Code EAR99 EAR99
Date Of Intro 1997-07-11
Samacsys Manufacturer Nexperia
Additional Feature BUILT IN BIAS RESISTOR RATIO IS 1 BUILT-IN BIAS RESISTOR RATIO IS 1
Collector Current-Max (IC) 0.1 A 0.1 A
Collector-Base Capacitance-Max 2.5 pF
Collector-Emitter Voltage-Max 50 V 50 V
Configuration SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR
DC Current Gain-Min (hFE) 60 60
JESD-30 Code R-PDSO-G6 R-PDSO-G6
JESD-609 Code e3 e3
Moisture Sensitivity Level 1 1
Number of Elements 2 2
Number of Terminals 6 6
Operating Temperature-Max 150 °C 150 °C
Operating Temperature-Min -55 °C
Package Body Material PLASTIC/EPOXY PLASTIC/EPOXY
Package Shape RECTANGULAR RECTANGULAR
Package Style SMALL OUTLINE SMALL OUTLINE
Peak Reflow Temperature (Cel) 260 260
Polarity/Channel Type NPN AND PNP NPN AND PNP
Power Dissipation-Max (Abs) 0.3 W 0.3 W
Reference Standard IEC-60134
Surface Mount YES YES
Terminal Finish TIN Tin (Sn)
Terminal Form GULL WING GULL WING
Terminal Position DUAL DUAL
Time@Peak Reflow Temperature-Max (s) 30 30
Transistor Application SWITCHING SWITCHING
Transistor Element Material SILICON SILICON
Transition Frequency-Nom (fT) 230 MHz
VCEsat-Max 0.15 V
Base Number Matches 3 2
Part Package Code TSSOP
Package Description PLASTIC, SC-88, 6 PIN
Pin Count 6
Manufacturer Package Code SOT363
Qualification Status Not Qualified

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Compare PUMD2,115 with alternatives