IDT74LVC827APG8 vs 74LVC827APW-T feature comparison

IDT74LVC827APG8 Integrated Device Technology Inc

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74LVC827APW-T Philips Semiconductors

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Rohs Code No No
Part Life Cycle Code Obsolete Transferred
Ihs Manufacturer INTEGRATED DEVICE TECHNOLOGY INC PHILIPS SEMICONDUCTORS
Part Package Code TSSOP
Package Description TSSOP, TSSOP, TSSOP24,.25
Pin Count 24
Reach Compliance Code compliant unknown
HTS Code 8542.39.00.01 8542.39.00.01
Additional Feature WITH DUAL OUTPUT ENABLE
Family LVC/LCX/Z
JESD-30 Code R-PDSO-G24 R-PDSO-G24
Length 7.8 mm
Logic IC Type BUS DRIVER BUS DRIVER
Number of Bits 10 10
Number of Functions 1 1
Number of Ports 2
Number of Terminals 24 24
Operating Temperature-Max 85 °C 85 °C
Operating Temperature-Min -40 °C -40 °C
Output Characteristics 3-STATE 3-STATE
Output Polarity TRUE TRUE
Package Body Material PLASTIC/EPOXY PLASTIC/EPOXY
Package Code TSSOP TSSOP
Package Shape RECTANGULAR RECTANGULAR
Package Style SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Cel) NOT SPECIFIED
Propagation Delay (tpd) 7.1 ns
Qualification Status Not Qualified Not Qualified
Seated Height-Max 1.2 mm
Supply Voltage-Max (Vsup) 3.6 V
Supply Voltage-Min (Vsup) 2.7 V
Supply Voltage-Nom (Vsup) 3.3 V 3.3 V
Surface Mount YES YES
Technology CMOS CMOS
Temperature Grade INDUSTRIAL INDUSTRIAL
Terminal Form GULL WING GULL WING
Terminal Pitch 0.65 mm 0.635 mm
Terminal Position DUAL DUAL
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Width 4.4 mm
Base Number Matches 1 2
Control Type ENABLE LOW
JESD-609 Code e0
Max I(ol) 0.024 A
Package Equivalence Code TSSOP24,.25
Packing Method TR
Prop. Delay@Nom-Sup 7 ns
Terminal Finish Tin/Lead (Sn/Pb)

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