HD74LVC540T vs 74LCX540WMX feature comparison

HD74LVC540T Renesas Electronics Corporation

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74LCX540WMX Fairchild Semiconductor Corporation

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Part Life Cycle Code Transferred Transferred
Ihs Manufacturer RENESAS ELECTRONICS CORP FAIRCHILD SEMICONDUCTOR CORP
Part Package Code TSSOP SOIC
Package Description TSSOP, 0.300 INCH, LEAD FREE, MS-013AC, SOIC-20
Pin Count 20 20
Reach Compliance Code compliant compliant
HTS Code 8542.39.00.01 8542.39.00.01
Additional Feature WITH DUAL OUTPUT ENABLE WITH DUAL OUTPUT ENABLE
Family LVC/LCX/Z LVC/LCX/Z
JESD-30 Code R-PDSO-G20 R-PDSO-G20
Length 6.5 mm 12.8 mm
Logic IC Type BUS DRIVER BUS DRIVER
Number of Bits 8 8
Number of Functions 1 1
Number of Ports 2 2
Number of Terminals 20 20
Operating Temperature-Max 85 °C 85 °C
Operating Temperature-Min -40 °C -40 °C
Output Characteristics 3-STATE 3-STATE
Output Polarity INVERTED INVERTED
Package Body Material PLASTIC/EPOXY PLASTIC/EPOXY
Package Code TSSOP SOP
Package Shape RECTANGULAR RECTANGULAR
Package Style SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE
Propagation Delay (tpd) 9 ns 7.8 ns
Qualification Status Not Qualified Not Qualified
Seated Height-Max 1.1 mm 2.65 mm
Supply Voltage-Max (Vsup) 5.5 V 3.6 V
Supply Voltage-Min (Vsup) 2 V 2 V
Surface Mount YES YES
Technology CMOS CMOS
Temperature Grade INDUSTRIAL INDUSTRIAL
Terminal Form GULL WING GULL WING
Terminal Pitch 0.65 mm 1.27 mm
Terminal Position DUAL DUAL
Width 4.4 mm 7.5 mm
Base Number Matches 1 1
Pbfree Code Yes
Rohs Code Yes
Manufacturer Package Code 20LD, SOIC, JEDEC MS013, .300", WIDE BODY
ECCN Code EAR99
Control Type ENABLE LOW
JESD-609 Code e3
Load Capacitance (CL) 50 pF
Max I(ol) 0.024 A
Moisture Sensitivity Level 1
Package Equivalence Code SOP20,.4
Packing Method TR
Peak Reflow Temperature (Cel) 260
Prop. Delay@Nom-Sup 6.5 ns
Supply Voltage-Nom (Vsup) 2.5 V
Terminal Finish MATTE TIN
Time@Peak Reflow Temperature-Max (s) 30

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